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ST72325AR7-Auto Datasheet(PDF) 171 Page - STMicroelectronics

Part # ST72325AR7-Auto
Description  SCI asynchronous serial interface
PDF  243 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72325AR7-Auto Datasheet(HTML) 171 Page - STMicroelectronics

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ST72325xxx-Auto
I2C bus interface (I2C)
Doc ID 13770 Rev 3
171/243
16.7.3
I2C status register 2 (SR2)
1M/SL
Master/Slave
This bit is set by hardware as soon as the interface is in Master mode (writing
START = 1). It is cleared by hardware after detecting a Stop condition on the bus or
a loss of arbitration (ARLO = 1). It is also cleared when the interface is disabled
(PE = 0).
0: Slave mode
1: Master mode
0SB
Start bit (Master mode)
This bit is set by hardware as soon as the Start condition is generated (following a
write START = 1). An interrupt is generated if ITE = 1. It is cleared by software
reading SR1 register followed by writing the address byte in DR register. It is also
cleared by hardware when the interface is disabled (PE = 0).
0: No Start condition
1: Start condition generated
Table 85.
SR1 register description (continued)
Bit
Name
Function
SR2
Reset value: 0000 0000 (00h)
76
543
21
0
Reserved
AF
STOPF
ARLO
BERR
GCAL
-
RO
RORORO
RO
Table 86.
SR2 register description
Bit
Name
Function
7:5
-
Reserved. Forced to 0 by hardware.
4AF
Acknowledge failure
This bit is set by hardware when no acknowledge is returned. An interrupt is
generated if ITE = 1. It is cleared by software reading SR2 register or by hardware
when the interface is disabled (PE = 0).
The SCL line is not held low while AF = 1 but by other flags (SB or BTF) that are set
at the same time.
0: No acknowledge failure
1: Acknowledge failure
Note: When an AF event occurs, the SCL line is not held low; however, the SDA line
can remain low if the last bits transmitted are all 0. It is then necessary to release
both lines by software.
3STOPF
Stop detection (Slave mode)
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK = 1). An interrupt is generated if ITE = 1. It is cleared by
software reading SR2 register or by hardware when the interface is disabled
(PE = 0).
The SCL line is not held low while STOPF = 1.
0: No Stop condition detected
1: Stop condition detected



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