STM32F398VE datasheet(125/151 Pages) STMICROELECTRONICS

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STM32F398VE

Electrical characteristics

142

Note:

Refer to theI2S section in RM0316 Reference Manual for more details about the sampling

frequency (Fs), fMCK, fCK, DCK values reflect only the digital peripheral behavior, source

clock precision might slightly change the values DCK depends mainly on ODD bit value.

Digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max

(I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max supported for each mode/condition.

tv(WS)

WS valid time

Master mode

th(WS)

WS hold time

Master mode

tsu(WS)

WS setup time

Slave mode

th(WS)

WS hold time

Slave mode

tsu(SD_MR)

Data input setup time

Master receiver

tsu(SD_SR)

Slave receiver

th(SD_MR)

Data input hold time

Master receiver

th(SD_SR)

Slave receiver

2.5

tv(SD_ST)

Data output valid time

Slave transmitter



(after enable edge)

-50

tv(SD_MT)

Master transmitter

(after enable edge)

-22

th(SD_ST)

Data output hold time

Slave transmitter (after

enable edge)

th(SD_MT)

Master transmitter

(after enable edge)

1. Data based on characterization results, not tested in production.

2. 256xFs maximum is 36 MHz (APB1 Maximum frequency)

Table 72. I2S characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Max

Unit

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