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STM32F398VE Datasheet(PDF) 128 Page - STMicroelectronics |
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STM32F398VE Datasheet(HTML) 128 Page - STMicroelectronics |
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128 / 151 page ![]() Electrical characteristics STM32F398VE 128/151 DocID027227 Rev 2 fS(1) Sampling rate Resolution = 12 bits, Fast Channel 0.01 - 5.14 MSPS Resolution = 10 bits, Fast Channel 0.012 - 6 Resolution = 8 bits, Fast Channel 0.014 - 7.2 Resolution = 6 bits, Fast Channel 0.0175 - 9 fTRIG(1) External trigger frequency fADC = 72 MHz Resolution = 12 bits -- 5.14 MHz Resolution = 12 bits - - 14 1/fADC VAIN Conversion voltage range(2) -0 - VREF+ V RAIN(1) External input impedance - - - 100 k CADC(1) Internal sample and hold capacitor -- 5 - pF tSTAB(1) Power-up time - 0 0 1 µs tCAL(1) Calibration time fADC = 72 MHz 1.56 µs - 112 1/fADC tlatr(1) Trigger conversion latency Regular and injected channels without conversion abort CKMODE = 00 1.5 2 2.5 1/fADC CKMODE = 01 - - 2 1/fADC CKMODE = 10 - - 2.25 1/fADC CKMODE = 11 - - 2.125 1/fADC tlatrinj(1) Trigger conversion latency Injected channels aborting a regular conversion CKMODE = 00 2.5 3 3.5 1/fADC CKMODE = 01 - - 3 1/fADC CKMODE = 10 - - 3.25 1/fADC CKMODE = 11 - - 3.125 1/fADC tS(1) Sampling time fADC = 72 MHz 0.021 - 8.35 µs - 1.5 - 601.5 1/fADC TADCVREG _STUP (1) ADC Voltage Regulator Start-up time -- - 10 µs tCONV(1) Total conversion time (including sampling time) fADC = 72 MHz Resolution = 12 bits 0.19 - 8.52 µs Resolution = 12 bits 14 to 614 (tS for sampling + 12.5 for successive approximation) 1/fADC 1. Data guaranteed by design, not tested in Production. 2. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pinouts and pin description for further details. Table 73. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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