PC87334VJG datasheet(4/102 Pages) NSC

4 / 102 page

Table of Contents (Continued)

60 SERIAL PORTS

61 Serial Port Registers

62 Line Control Register (LCR)

63 Programmable Baud Rate Generator

64 Line Status Register (LSR)

65 FIFO Control Register

66 Interrupt Identification Register (IIR)

67 Interrupt Enable Register (IER)

68 MODEM Control Register (MCR)

69 MODEM Status Register (MSR)

610 Scratchpad Register (SCR)

70 PARALLEL PORT

71 Introduction

72 Data Register (DTR)

73 Status Register (STR)

74 Control Register (CTR)

75 Enhanced Parallel Port Operation

76 Extended Capabilities Parallel Port (ECP)

761 Introduction

762 Software Operation

77 Register Definitions

78 Software Controlled Data Transfer (Modes 000 and

001)

79 Automatic Data Transfer (Modes 010 and 011)

791 Forward Direction (Bit 5 of DCRe0)

792 ECP (Forward) Write Cycle

793 Backward Direction (bit 5 of DCR is 1)

794 ECP (Backward) Read Cycle

710 FIFO Test Access (Mode 110)

711 Configuration Registers Access (Mode 111)

712 Interrupt Generation

80 INTEGRATED DEVICE ELECTRONICS

INTERFACE (IDE)

81 Introduction

82 IDE Signals

90 SERIAL INFRARED INTERFACE (SIR)

100 ELECTRICAL CHARACTERISTICS

101 DC Electrical Characteristics

102 DC Electrical Characteristics

103 AC Electrical Characteristics

1031 AC Test Conditions

1032 Clock Timing

1033 Microprocessor Interface Timing

1034 Baud Out Timing

1035 Transmitter Timing

1036 Receiver Timing

1037 MODEM Control Timing

1038 DMA Timing

1039 Reset Timing

10310 Write Data Timing

10311 Drive Control Timing

10312 Read Data Timing

10313 IDE Timing

10314 Parallel Port Timing

10315 Enhanced Parallel Port Timing

10316 Extended Capabilities Port Timing

10317 3F3 Read Timing

PC87334VJG Datasheet(PDF) 4 Page - National Semiconductor (TI)

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