S3A3 datasheet(120/139 Pages) RENESAS

120 / 139 page

R01DS0307EU0100 Rev.1.00

Page 120 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

2.12.3

Capacitor Split Method

[1/3 Bias Method]

Note 1.

This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).

Note 2.

This is a capacitor that is connected between voltage pins used to drive the LCD.

C1: A capacitor connected between CAPH and CAPL

C2: A capacitor connected between VL1 and GND

C3: A capacitor connected between VL2 and GND

C4: A capacitor connected between VL4 and GND

C1 = C2 = C3 = C4 = 0.47 μF ± 30%.

Figure 2.92

LCD reference voltage setup time, voltage boosting wait time, and capacitor split wait time

2.13

Comparator Characteristics

Note:

When 8-bit DAC output is used as the reference voltage, the offset voltage increases up to 2.5 x VCC/256.

Note:

In window mode, you must satisfy the following condition: Vref1 - Vref0 > 0.2 V.

Table 2.72

Internal voltage boosting method LCD characteristics

Conditions: VCC = 2.2 V to 5.5 V

Parameter

Symbol Conditions

Min

Typ

Max

Unit

Test

conditions

VL4 voltage*1

VL4

C1 to C4 = 0.47 μF*2

-VCC

VL2 voltage*1

VL2

C1 to C4 = 0.47 μF*2

2/3 × VL4 - 0.07 2/3 × VL4

2/3 × VL4 + 0.07

VL1 voltage*1

VL1

C1 to C4 = 0.47 μF*2

1/3 × VL4 - 0.08 1/3 × VL4

1/3 × VL4 + 0.08

Capacitor split wait time*1

tWAIT

100

Figure 2.92

Table 2.73

ACMPLP characteristics

Conditions: VCC = 1.8 to 5.5 V

Item

Symbol

Min

Typ

Max

Unit

Test conditions

Reference voltage range

Standard mode

VREF

VCC–1.4

Window mode

CMPREF1

VREFH

1.4

VCC

CMPREF0

VREFL

VCC–1.4

Input voltage range

VCC

Internal reference voltage

1.36

1.44

1.50

Output delay

High-speed mode

1.2

μs

VCC = 3.0

Slew rate of input

signal > 50 mV/μs

Low-speed mode

μs

Window mode

μs

Offset voltage

High-speed mode

Low-speed mode

Window mode

Operation stabilization wait time

Tcmp

100

μs-

MDSET0,

MDSET1

VLCON

LCDON

01b or 10b

00b

tVL1S

tVLWT, tWAIT

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