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S3A3 Datasheet(PDF) 126 Page - Renesas Technology Corp |
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S3A3 Datasheet(HTML) 126 Page - Renesas Technology Corp |
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126 / 139 page  R01DS0307EU0100 Rev.1.00 Page 126 of 139 Mar 7, 2017 S3A3 2. Electrical Characteristics Figure 2.96 JTAG TCK timing Figure 2.97 JTAG input/output timing Table 2.83 JTAG (debug) characteristics (2) Conditions: VCC = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 250 - - ns Figure 2.96 TCK clock high pulse width tTCKH 120 - - ns TCK clock low pulse width tTCKL 120 - - ns TCK clock rise time tTCKr -- 5 ns TCK clock fall time tTCKf -- 5 ns TMS setup time tTMSS 50 - - ns Figure 2.97 TMS hold time tTMSH 50 - - ns TDI setup time tTDIS 50 - - ns TDI hold time tTDIH 50 - - ns TDO data delay time tTDOD - - 150 ns TCK tTCKcyc tTCKH tTCKf tTCKL tTCKr TCK TMS TDI TDO tTMSS tTMSH tTDIH tTDIS tTDOD |
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