R5F117BA datasheet(39/102 Pages) RENESAS

39 / 102 page

RL78/I1D

2. ELECTRICAL SPECIFICATIONS

R01DS0244EJ0220 Rev. 2.20

Page 39 of 99

Feb 20, 2017

Note 1.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when

DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 2.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when

DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 3.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from

SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 4.

C is the load capacitance of the SCKp and SOp output lines.

Caution

Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using

port input mode register g (PIMg) and port output mode register g (POMg).

Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5)

Remark 2.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00))

(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,

corresponding CSI00 only)

(TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main)

Mode

LS (low-speed main)

Mode

LP (Low-power main)

mode

LV (low-voltage main)

Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SCKp cycle time

tKCY1

≥ fCLK/2

83.3

250

2000

500

SCKp high-/low-level width

tKL1

tKCY1/2

- 10

tKCY1/2

- 50

tKCY1/2

- 50

tKCY1/2

- 50

SIp setup time (to SCKp↑)

Note 1

tSIK1

110

SIp hold time (from SCKp↑)

Note 2

tKSI1

Delay time from SCKp↓ to

SOp output Note 3

tKSO1

C = 20 pF

Note 4

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