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CS43199 Datasheet(PDF) 73 Page - Cirrus Logic

Part # CS43199
Description  130-dB, 32-Bit High-Performance DAC
PDF  111 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43199 Datasheet(HTML) 73 Page - Cirrus Logic

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DS1113F1
73
CS4399
7 Register Descriptions
7 Register Descriptions
All registers are read/write, except for the device’s ID, revision, and status registers, which are read only. The following
tables describe bit assignments. The default state of each bit after a power-up sequence or reset is listed in each bit
description. All reserved bits must maintain their default state.
7.1 Global Registers
7.1.1
Device ID A and B
Address 0x10000
R/O
76543210
DEVIDA
DEVIDB
Default
01000011
Bits
Name
Description
7:4
DEVIDA
Part number first digit: 4
3:0
DEVIDB
Part number second digit: 3
7.1.2
Device ID C and D
Address 0x10001
R/O
76543210
DEVIDC
DEVIDD
Default
10011001
Bits
Name
Description
7:4
DEVIDC
Part number third digit: 9
3:0
DEVIDD
Part number fourth digit: 9
7.1.3
Revision ID
Address 0x10004
R/O
76543210
AREVID
MTLREVID
Default
xxxxxxxx
Bits
Name
Description
7:4
AREVID
Alpha revision. AREVID and MTLREVID form the complete device revision ID (e.g., A0, B2).
3:0
MTLREVID
Metal revision. AREVID and MTLREVID form the complete device revision ID (e.g., A0, B2).
7.1.4
Subrevision ID
Address 0x10005
R/O
76543210
SUBREVID
Default
xxxxxxxx
Bits
Name
Description
7:0
SUBREVID
Subrevision level.
7.1.5
System Clocking Control
Address 0x10006
R/W
76543210
—
MCLK_INT
MCLK_SRC_SEL
Default
00000110
Bits
Name
Description
7:3
—
Reserved
2
MCLK_INT
The frequency of internal MCLK.
0 Internal MCLK is expected to be 24.576 MHz
1 (Default) Internal MCLK is expected to be 22.5792 MHz



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