CS43199 datasheet(23/111 Pages) CIRRUS

23 / 111 page

DS1113F1

CS4399

4.2 Analog Outputs

The CS4399 provides an analog output that is derived from the digital audio input ports. This section describes the general

flow of the analog outputs.

4.2.1

Analog Output Signal Flow

The CS4399 signal flow is shown in Fig. 4-1.

Figure 4-1. Analog Output Signal Flow

The CS4399 has 2 settings of full scale voltage, which are determined by OUT_FS[1:0]. The proper full scale voltage must

be set first, and the digital volume settings is used to control signal levels.

The CS4399 digital volume control allows independent control of the signal level in 1/2 dB increments from 0 dB

(0b0000 0000) to –127 dB (0b1111 1110) by using x_VOLUME_y (where "x" is either PCM or DSD; "y" is either A or B)

volume changes are implemented as dictated by PCM_SZC[1:0] and DSD_SZC in the signal control register (see

Section 7.4.3 and Section 7.5.5). If soft ramping is enabled, gain and attenuation changes are carried out by incrementally

changing the volume level in 1/8-dB steps, from the previous level to the new level. For PCM, when PCM_SZC[1:0] = 2,

the volume level changes at an approximate rate of 1 dB/ms. For DSD, when DSD_SZC = 1, the volume level also

changes at an approximate rate of 1 dB/ms during power up or when coming out of a mute state (DSD_MUTE_x = 1). Note

that when recovering from an error state caused by static DSD data (DSD_STUCK_INT = 1), the volume output will

resume at the level specified in DSD_VOLUME_x registers. Both channels can be inverted by setting the INV_A and INV_

B bits.

The CS4399 provides individual ramp-up control option (from the global soft ramp settings) for a specific scenario. The

PCM_RAMP_DOWN bit is for the scenario when the interpolation filter switches during PCM playback. Refer to the

The CS4399 can mute both channels simultaneously or independently. Also, it can auto-mute on both PCM stream and

DSD stream when mute pattern is identified (defined in PCM_AMUTE and DSD_AMUTE). Additional signal and mute

control options can be found in Section 7.4.3 and Section 7.5.5.

The CS4399 has an independent set of controls for the DSD processor path as shown in Fig. 4-1. The DSD processor

also offers the control bit SIGCTL_DSDEQPCM, which maps the PCM_x setting to DSD_x setting, once enabled. As a

result, some of the DSD_x register settings are ignored. The registers affected are DSD_VOL_BEQA, DSD_SZC, DSD_

AMUTE, DSD_AMUTE_BEQA, DSD_MUTE_A, DSD_MUTE_B, DSD_INV_A, DSD_INV_B, DSD_SWAP_CHAN, and

Multibit



Modulator

Multibit



Modulator

Interpolation

Filter &

Volume

Control

Interpolation

Filter &

Volume

Control

AOUTA

AOUTB

DSD

Processor

DoP to

DSD

Engine

Audio

Source

REFB

REFA

DoP

DSD

DAC and

Filter

DAC and

Filter



DAC_OVFL_INT p. 90

DSD_PRC_SRC p. 85

PCM_SZC p. 88

PCM_RAMP_DOWN p. 88

PCM_VOLUME_B p. 87

PCM_VOLUME_A p. 87

PCM_INV_A p. 88

PCM_INV_B p. 88

PCM_VOL_BEQA p. 88

PCM_AMUTE p. 88

PCM_AMUTEBEQA p. 88

PCM_MUTE_A p. 88

PCM_MUTE_B p. 88

FILTER_SLOW_FASTB p. 87

PHCOMP_LOWLATB p. 87

HIGH_PASS p. 87

DEEMP_ON p. 87

NOS p. 87

MIX_PCM_PREP p. 85

MIX_PCM_DSD p. 86

OUT_FS p. 86

DSD_EN p. 85

DSD_SPEED p. 85

STA_DSD_DET p. 85

INV_DSD_DET p. 85

DSD_VOLUME_B p. 84

DSD_VOLUME_A p. 84

DSD_INV_A p. 86

DSD_INV_B p. 86

DSD_VOL_BEQA p. 84

DSD_AMUTE p. 84

DSD_MUTE_A p. 84

DSD_MUTE_B p. 84

DSD_ZERODB p. 86

DSD_HPF_EN p. 86

OUT_FS p. 86

DSD_SZC p. 84

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