CC3220MODASM2MONR datasheet(32/100 Pages) TI1

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Terminal Configuration and Functions

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Product Folder Links: CC3220MOD CC3220MODA

CC3220MOD, CC3220MODA

SWRS206B – MARCH 2017 – REVISED AUGUST 2017

www.ti.com

NOTE

The ADC inputs are tolerant up to 1.8 V (see Section 5.14.5.6 for further details on the useable range of the ADC). The digital pads can tolerate

up to 3.6 V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital I/Os

corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 47],

S8 [Pin 48], S9 [Pin 49], and S10 [Pin 50]). For more information, see Drive Strength and Reset States for Analog-Digital Multiplexed Pins.

4.5

Drive Strength and Reset States for Analog-Digital Multiplexed Pins

Table 4-5 describes the use, drive strength, and default state of analog- and digital-multiplexed pins at first-time power up and reset (nRESET

pulled low).

Table 4-5. Drive Strength and Reset States for Analog-Digital Multiplexed Pins

BOARD LEVEL CONFIGURATION AND USE

DEFAULT STATE AT FIRST POWER UP OR

FORCED RESET

STATE AFTER CONFIGURATION OF ANALOG

SWITCHES (ACTIVE, LPDS, and HIB POWER

MODES)

MAXIMUM

EFFECTIVE DRIVE

STRENGTH (mA)

Connected to the enable pin of the RF switch

(ANT_SEL1). Other use is not recommended.

Analog is isolated. The digital I/O cell is also

isolated.