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DAC38RF83IAAV Datasheet(PDF) 45 Page - Texas Instruments

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Part # DAC38RF83IAAV
Description  Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL
PDF  155 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC38RF83IAAV Datasheet(HTML) 45 Page - Texas Instruments

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DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
www.ti.com
SLASEA3C – DECEMBER 2016 – REVISED JULY 2017
DAC38RF83 DAC38RF93
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Table 9. JESD204B Formats for DAC38RFxx (continued)
L-M-F-S-Hd
1 TX
L-M-F-S-Hd
2 TX
Frame
Format
Input
Resolution
IQ Pairs
Per DAC
Interp
Input Rate
Max
(MSPS)
fDAC Max
(MSPS)
DAC38RF83,
DAC38RF80
DAC38RF93,
DAC38RF90
DAC38RF85
(1 TX only)
DAC38RF84
(1 TX only)
24410
48410
1 TX:
Table 19
2 TX:
Table 20
16
2
16
312.5
5000
√
√
√
16
2
24
312.5
7500
√
√
√
24310
48310
1 TX:
Table 21
2 TX:
Table 22
12
2
24
375
9000
√
√
√
Table 10. JESD204B Frame Format for LMFSHd = 82121
# un bits
4
8
# en bits
5
10
Nibble
1
2
lane RX0
i0[15:8]
lane RX1
i0[7:0]
lane RX2
i1[15:8]
lane RX3
i1[7:0]
lane RX4
q0[15:8]
lane RX5
q0[7:0]
lane RX6
q1[15:8]
lane RX7
q1[7:0]
Table 11. JESD204B Frame Format for LMFSHd = 42111
# un bits
4
8
# en bits
5
10
Nibble
1
2
lane RX0
i0[15:8]
lane RX1
i0[7:0]
lane RX2
q0[15:8]
lane RX3
q0[7:0]
(1)
DAC A, I sample 0, MSB byte
(2)
DAC A, I sample 0, LSB byte
Table 12. JESD204B Frame Format for LMFSHd = 84111
# un bits
4
8
# en bits
5
10
Nibble
1
2
lane RX0
A-i0[15:8](1)
lane RX1
A-i0[7:0](2)
lane RX2
A-q0[15:8]
lane RX3
A-q0[7:0]
lane RX4
B-i0[15:8]
lane RX5
B-i0[7:0]
lane RX6
B-q0[15:8]
lane RX7
B-q0[7:0]



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