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DAC38RF83IAAV Datasheet(PDF) 91 Page - Texas Instruments

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Part # DAC38RF83IAAV
Description  Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL
PDF  155 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC38RF83IAAV Datasheet(HTML) 91 Page - Texas Instruments

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DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
www.ti.com
SLASEA3C – DECEMBER 2016 – REVISED JULY 2017
DAC38RF83 DAC38RF93
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
8.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
Figure 91. Multi-DUC Configuration (Mixers) Register (MULTIDUC_CFG2)
15
14
13
12
11
10
9
8
0
0
0
0
0
1
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 56. MULTIDUC_CFG2 Field Descriptions
Bit
Field
Type
Reset
Description
15:14
DAC_BITWIDTH
R/W
0b00
Determines the bit width of the data going to the DAC
00: 14 bits
01: 14 bits
10: 12 bits
11: 11 bits
13
ZERO_INVLD_DATA
R/W
1
When asserted; the data from the JESD block is zeroed in the
mapper to prevent goofy output from the DAC. For test purposes
this bit should be desasserted
12
SHORTTEST_ENA
R/W
0
Turns on the JESD SHORT pattern test (5.1.6.2)
11
Reserved
R/W
0
Reserved
10
Reserved
R/W
1
Reserved
9
MIXERAB_ENA
R/W
0
Turns on the mixer for the A and B streams
8
MIXERCD_ENA
R/W
0
Turns on the mixer for the C and D streams
7
MIXERAB_GAIN
R/W
0
Adds 6dB of gain when asserted
6
MIXERCD_GAIN
R/W
0
Adds 6dB of gain when asserted
5
NCOAB_ENA
R/W
0
When high the full NCO block is turned on.
4
NCOCD_ENA
R/W
0
When high the full NCO block is turned on.
3:2
Reserved
R/W
00
Reserved
1
TWOS
R/W
1
When asserted the chip is expecting 2's complement data is
arriving through the JESD; otherwise offset binary is expected
0
Reserved
R/W
0
Reserved



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