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RT5509WSC Datasheet(PDF) 32 Page - Richtek Technology Corporation |
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RT5509WSC Datasheet(HTML) 32 Page - Richtek Technology Corporation |
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32 / 58 page ![]() RT5509 Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5509-00 August 2017 32 ADDR Byte Bits R/W Name Description Default 0x09 1 7 R/W ORDER_DSP 0 : EQ BWE DRC 1 : DRC EQ BWE 1 6 R/W STRSYNC Gain Synchronize in stereo mode 0 : Don’t sync 1 : Sync to use minimum gain from two channels 0 5 R/W LMTEN Limiter Enable 0 : Disable 1 : Enable 0 4 R/W ALCEN ALC gain Control enable 0 : disable 1 : enable 0 3 R/W MBDRCEN Multi-Band DRC Enable 0 : Disable 1 : Enable 0 2 R/W BWEEN LPF + BWE enable 0 : disable, output zero at lower branch 1 : enable 0 1 R/W HPFEN HPF enable 0 : Bypass at upper branch 1 : enable 0 0 R/W BQEN 10 Band BQ Enable 0 : Bypass 10 band BQ 1 : Enable 10 band BQ 0 0x10 1 7:3 Reserved 0 2:0 R/W VBCPS Clip threshold setting 000 : 4.0V 001 : 3.75V 010 : 3.6V 011 : 3.45V 100 : 3.3V 101 : 3.15V 110 : 3V 111 : 2.85V 0 |
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