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TLV62568DRLR Datasheet(PDF) 7 Page - Texas Instruments

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Part # TLV62568DRLR
Description  1-A High Efficiency Synchronous Buck Converter in SOT Package
PDF  26 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLV62568DRLR Datasheet(HTML) 7 Page - Texas Instruments

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Control Logic
Soft Start
Thermal
Shutdown
UVLO
Gate
Drive
GND
FB
EN
SW
Modulator
TOFF
GND
Zero Current Detect
Peak Current Detect
+
_
VREF
VSW
VIN
+
±
GND
VPG
VFB
VIN
PG
Power Good feature is only available in TLV62568P
Copyright Ú 2016, Texas Instruments Incorporated
7
TLV62568, TLV62568P
www.ti.com
SLVSD89A – NOVEMBER 2016 – REVISED APRIL 2017
Product Folder Links: TLV62568 TLV62568P
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The TLV62568 is a high-efficiency synchronous step-down converter. The device operates with an adaptive off-
time with peak current control scheme. The device operates at typically 1.5-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the
required off time for the low-side MOSFET. It makes the switching frequency relatively constant regardless of the
variation of input voltage, output voltage, and load current.
7.2 Functional Block Diagram
Figure 4. TLV62568 Functional Block Diagram
7.3 Feature Description
7.3.1 Power Save Mode
The device automatically enters Power Save Mode to improve efficiency at light load when the inductor current
becomes discontinuous. In Power Save Mode, the converter reduces switching frequency and minimizes current
consumption. In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect
is minimized by increasing the output capacitor.
7.3.2 100% Duty Cycle Low Dropout Operation
The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input
voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:
VIN(MIN) = VOUT + IOUT x (RDS(ON) + RL)
where
•
RDS(ON) = High side FET on-resistance
•
RL = Inductor ohmic resistance (DCR)
(1)
7.3.3 Soft Startup
After enabling the device, internal soft startup circuitry ramps up the output voltage which reaches nominal output
voltage during a startup time. This avoids excessive inrush current and creates a smooth output voltage rise
slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal
impedance.



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