7LPH

V ',9

D017

0.1V/DIV

0.5A/DIV

7LPH

V ',9

D018

0.1V/DIV

0.5A/DIV

7LPH

V ',9

D015

3V/DIV

1V/DIV

1A/DIV

7LPH

V ',9

D016

3V/DIV

1V/DIV

0.5A/DIV

13

TLV62568, TLV62568P

www.ti.com

SLVSD89A – NOVEMBER 2016 – REVISED APRIL 2017

Product Folder Links: TLV62568 TLV62568P

Submit Documentation Feedback

Copyright © 2016–2017, Texas Instruments Incorporated

Figure 16. Startup with Load

Figure 17. Startup with Load

Load Step 0.3 A to 1 A, 1A/µs slew rate

Figure 18. Load Transient

Load Step 0.3 A to 1 A, 1A/µs slew rate

C3 = 6.8 pF

Figure 19. Load Transient with a feed forward capacitor

9 Power Supply Recommendations

The power supply to the TLV62568 must have a current rating according to the supply voltage, output voltage

and output current.

10 Layout

10.1 Layout Guidelines

The PCB layout is an important step to maintain the high performance of the TLV62568 device.

•

The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the

power traces short. Routing these power traces direct and wide results in low trace resistance and low

parasitic inductance.

•

The low side of the input and output capacitors must be connected properly to the power GND to avoid a

GND potential shift.

•

The sense traces connected to FB are signal traces. Special care should be taken to avoid noise being

induced. Keep these traces away from SW nodes.

•

GND layers might be used for shielding.