AD7262

Data Sheet

Rev. B | Page 26 of 32

CS

31

32

33

34

35

30

22

21

20

19

DOUTA

THREE-STATE

THREE-

STATE

SCLK

12

45

46

47

XX

X

X

CS

SCLK

1

5

19

THREE-STATE

2

34

20

THREE-

STATE

18

21

29

30

31

THREE-STATE

THREE-

STATE

FIRST DATA BIT CLOCKED

OUT ON THIS EDGE

FIRST DATA BIT READ

ON THIS EDGE

Figure 35. Serial Interface Timing Diagram When Reading Data on the Falling SCLK Edge with a Slow SCLK Frequency