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HM628128ALP-7SL Datasheet(PDF) 7 Page - Hitachi Semiconductor

Part # HM628128ALP-7SL
Description  131,072-word X 8-bit High Speed CMOS Static RAM
PDF  13 Pages
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Manufacturer  HITACHI [Hitachi Semiconductor]
Direct Link  http://www.renesas.com/eng
Logo HITACHI - Hitachi Semiconductor

HM628128ALP-7SL Datasheet(HTML) 7 Page - Hitachi Semiconductor

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AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: 0.8 V to 2.4 V (HM628128A-7/8/10)
0 V to 3 V (HM628128A-5)
• Input rise and fall times: 5 ns
• Input and output timing reference levels: 1.5 V
• Output load: 1 TTL Gate and CL (100 pF) (HM628128A-7/8/10)
1 TTL Gate and CL (30 pF) (HM628128A-5) (Including scope & jig)
Read Cycle
HM628128A
-5
-7
-8
-10
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Read cycle time
tRC
55
—
70
—
85
—
100
—
ns
Address access time
tAA
—
55
—
70
—
85
—
100
ns
Chip selection to
tCO1
—
55
—
70
—
85
—
100
ns
output valid
tCO2
—
55
—
70
—
85
—
100
ns
Output enable to
tOE
—
30
—
35
—
45
—
50
ns
output valid
Chip selection to
tLZ1
5
—
10
—
10
—
10
—
ns
2, 3
output in low-Z
tLZ2
5
—
10
—
10
—
10
—
ns
2, 3
Output enable to
tOLZ
5
—
5
—
5
—
5
—
ns
2, 3
output in low-Z
Chip deselection to
tHZ1
0
20
0
25
0
30
0
35
ns
1, 2, 3
output in high-Z
tHZ2
0
20
0
25
0
30
0
35
ns
1, 2, 3
Output disable to
tOHZ
0
20
0
25
0
30
0
35
ns
1, 2, 3
output in high-Z
Output hold from
tOH
5
—
10
—
10
—
10
—
ns
address change
7
HM628128A Series



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