FDMF3035 datasheet(17/21 Pages) ONSEMI

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PCB Layout Guideline

Figure 30 and Figure 31 provide an example of single-

phase

layout

for

the

FDMF3035

and

critical

components. All of the high-current paths; such as VIN,

SW, VOUT, and GND coppers; should be short and

wide for low parasitic inductance and resistance. This

helps achieve a more stable and evenly distributed

current flow, along with enhanced heat radiation and

system performance.

Input ceramic bypass capacitors must be close to the

VIN and PGND pins. This reduces the high-current

power loop inductance and the input current ripple

induced by the power MOSFET switching operation.

The SW copper trace serves two purposes. In addition

to being the high-frequency current path from the SPS

package to the output inductor, it serves as a heat sink

for the low-side MOSFET. The trace should be short

and wide enough to present a low-impedance path for

the high-frequency, high-current flow between the SPS

and the inductor. The short and wide trace minimizes

electrical losses and SPS temperature rise. The SW

node is a high-voltage and high-frequency switching

node with high noise potential. Care should be taken to

minimize coupling to adjacent traces. Since this copper

trace acts as a heat sink for the low-side MOSFET,

balance using the largest area possible to improve SPS

cooling while maintaining acceptable noise emission.

An output inductor should be located close to the

FDMF3035 to minimize the power loss due to the SW

copper trace. Care should also be taken so the inductor

dissipation does not heat the SPS.

PowerTrench

® MOSFETs are used in the output stage

and are effective at minimizing ringing due to fast

switching. In most cases, no RC snubber on SW node is

required. If a snubber is used, it should be placed close

to the SW and PGND pins. The resistor and capacitor of

the snubber must be sized properly to not generate

excessive heating due to high power dissipation.

Decoupling capacitors on PVCC, VCC, and BOOT

capacitors should be placed as close as possible to the

PVCC ~ PGND, VCC ~ AGND, and BOOT ~ PHASE pin

pairs to ensure clean and stable power supply. Their

routing traces should be wide and short to minimize

parasitic PCB resistance and inductance.

The board layout should include a placeholder for small-

value series boot resistor on BOOT ~ PHASE. The boot-

loop size, including series RBOOT and CBOOT, should be

as small as possible.

A boot resistor may be required when the SPS is

operating above 15 V VIN and it is effective to control the

high-side MOSFET turn-on slew rate and SW voltage

overshoot. RBOOT can improve noise operating margin in

synchronous buck designs that may have noise issues

due to ground bounce or high positive and negative VSW

ringing. Inserting a boot resistance lowers the SPS

module efficiency. Efficiency versus switching noise

must be considered. RBOOT values from 0.5  to 4.7 

are typically effective in reducing VSW overshoot.

The VIN and PGND pins handle large current transients

with frequency components greater than 100 MHz. If

possible, these pins should be connected directly to the

VIN and board GND planes. The use of thermal relief

traces in series with these pins is not recommended

since this adds extra parasitic inductance to the power

path. This added inductance in series with either the

VIN or PGND pin degrades system noise immunity by

increasing positive and negative VSW ringing.

PGND pad and pins should be connected to the GND

copper plane with multiple vias for stable grounding.

Poor grounding can create a noisy and transient offset

voltage level between PGND and AGND. This could

lead to faulty operation of gate driver and MOSFETs.

Ringing at the BOOT pin is most effectively controlled

by close placement of the boot capacitor. Do not add

any additional capacitors between BOOT to PGND. This

may lead to excess current flow through the BOOT

diode, causing high power dissipation.

The FCCM pin integrates weak internal pull-up and pull-

down current sources. The current sources are used to

help hold the FCCM in the 3-state window. This pin

should not have any noise filter capacitors if actively

driven by a PWM controller. Do not float this pin.

Multiple vias should be placed on the VIN and VOUT

copper areas to interconnect nodes that are located on

multiple layers (top, inner, and bottom layers). The vias

help

evenly

distribute

current

flow

and

heat

conduction.

Care should be taken when routing the copper pour area

and via placement on the SW copper. A large SW node

copper pour can result in excessive parasitic inductance

and capacitance, which can increase switching noise.

However, the copper pour area and via placement can

affect the efficiency and thermal performance, where a

large copper pour can help decrease thermal resistance

and parasitic resistance. If possible, place the SW node

copper on the top layer with no vias on the SW copper to

minimize switch node parasitic noise. If multiple SW node

layers are needed, vias should be relatively large and of

reasonably low inductance.

Critical high-frequency components; such as RBOOT,

CBOOT, RC snubber, and bypass capacitors; should be

located as close to the respective SPS module pins as

possible on the top layer of the PCB. If this is not

feasible, they can be placed on the board bottom side

and their pins connected from bottom to top through a

network of low-inductance vias.

FDMF3035 Datasheet(PDF) 17 Page - ON Semiconductor

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