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SLG46170 Datasheet(PDF) 74 Page - Dialog Semiconductor |
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SLG46170 Datasheet(HTML) 74 Page - Dialog Semiconductor |
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74 / 87 page ![]() 000-0046170-103 Page 73 of 86 SLG46170 reg<717:715> Counter/delay0 Clock Source Select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 7 Overflow reg<731:718> Counter0 Control Data/Delay0 Time Control 1-16384: (delay time = (counter control data +2) /freq) reg<733:732> Delay0 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<734> Counter/Delay1 mode select 0: Delay Mode 1: Counter Mode reg<737:735> Counter/delay1 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 0 Overflow reg<751:738> Counter1 Control Data/Delay1 Time Control 1-16384: (delay time = (counter control data +2) /freq) reg<753:752> Delay1 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter reset) 10: Delay on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode reg<754> Counter/Delay2 Mode selection 0: Delay Mode 1: Counter Mode reg<757:755> Counter/delay2 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 1 Overflow reg<765:758> Counter2 Control Data/Delay2 Time Control 1-256: (delay time = (counter control data +2) /freq) reg<767:766> Delay2 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter re- set) 10: Delay on rising edge only (for delay & counter re- set) 11: No delay on either falling or rising edges / high level reset for counter mode reg<768> Counter/Delay3 Mode selection 0: Delay Mode 1: Counter Mode Register Bit Address Signal Function Register Bit Definition |
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