SLG46170 datasheet(81/87 Pages) DIALOG

81 / 87 page

000-0046170-103

Page 80 of 86

SLG46170

reg<979>

NVM data read disable

0: Disable (program data can be read)

1: Enable (Program data cannot be read)

reg<980>

NVM power down

0: None (or programming enable)

1: Power Down (or programming disable)

reg<981>

GPIO quick charge enable

0: Disable

1: Enable

reg<983: 982> Reserved

reg<991:984> Reserved

reg<999:992> 8-bit Pattern ID

reg<1001:1000>

Delay value select for programmable delay & edge de-

tector

(VDD 3.3V, typ)

00: 125 ns

01: 250 ns

10: 375 ns

11: 500 ns

reg<1003:1002>

Select the edge mode of programmable delay & edge

detector

00: rising edge detector

01: falling edge detector

10: both edge detector

11: both edge delay

reg<1004>

Select edge detector output mode

0: edge detector output

1: delayed edge detector output

reg<1005>

Select polarity of filter_0 output

0: non-inverted

1: inverted

reg<1006>

Select polarity of filter_1 output

0: non-inverted

1: inverted

reg<1007>

Reserved

reg<1013:1008 > Reserved

reg<1014>

Reserved

reg<1015>

Reserved

reg<1023:1016> Reserved

Address

Signal Function

SLG46170 Datasheet(PDF) 81 Page - Dialog Semiconductor

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