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AD7293BCPZ Datasheet(PDF) 44 Page - Analog Devices

Part # AD7293BCPZ
Description  12-Bit Power Amplifier Current Controller
PDF  78 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7293BCPZ Datasheet(HTML) 44 Page - Analog Devices

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AD7293
Data Sheet
Rev. B | Page 44 of 78
Bit Number(s)
Bit Name
Description
D11
CL2_FR
0: Closed-Loop 2 fast ramp disable
1: Closed-Loop 2 fast ramp enable (default)
[D10:D8]
CL2_CAP_TRIM[2:0]
000: not applicable
001: 2.352 ms
010: 1.218 ms
011: 840 µs (default)
100: 650 µs
101: 538 µs
110: 462 µs
111: 408 µs
D7
CL1_FR
0: Closed-Loop 1 fast ramp disable
1: Closed-Loop 1 fast ramp enable (default)
[D6:D4]
CL1_CAP_TRIM[2:0]
000: not applicable
001: 2.352 ms
010: 1.218 ms
011: 840 µs (default)
100: 650 µs
101: 538 µs
110: 462 µs
111: 408 µs
D3
CL0_FR
0: Closed-Loop 0 fast ramp disable
1: Closed-Loop 0 fast ramp enable (default)
[D2:D0]
CL0_CAP_TRIM[2:0]
000: not applicable
001: 2.352 ms
010: 1.218 ms
011: 840 µs (default)
100: 650 µs
101: 538 µs
110: 462 µs
111: 408 µs
Table 51. Integrator Limit Active Status (INTLIMITx) and AVSS/AVDD Alarm Mask Register (Register 0x2F)
Bit Number(s)
Bit Name
Description
[D15:D12]
Reserved
Reserved
D11
INTLIMIT3
0: no masking (default)
1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or
if routed to ALERTx pins
D10
INTLIMIT2
0: no masking (default)
1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or
if routed to ALERTx pins
D9
INTLIMIT1
0: no masking (default)
1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or
if routed to ALERTx pins
D8
INTLIMIT0
0: no masking (default)
1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or
if routed to ALERTx pins
[D7:D1]
Reserved
Reserved
D0
AVSS/AVDD alarm
0: no masking (default)
1: masks alert



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