AD7293BCPZ datasheet(27/78 Pages) AD

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Data Sheet

AD7293

Rev. B | Page 27 of 78

target DAC code is set immediately. Depending on the overall

loop time constant, an additional settling time can be required

after the end of the ramp for the drain current to reach the

prescribed set point.

Figure 47. Programmable Ramp Time Representation

Fast Ramp Feature

To accelerate the initial settling of the closed loop, the fast ramp

feature can be enabled. When the ramp time register is programmed

to 0x0000, the ramp generator disables. In this mode, when the

current sense reading is less than 0x00F, the integrator time

constant is reduced to 408 µs, allowing the gate control voltage

to reach the PA threshold voltage as quickly as possible. When

above this current, the time constant automatically returns to its

programmed value. When a different switching threshold is

desired, use the current sense offset register to allow Code 0x00F to

represent a higher or lower current. This features may be useful to

prevent unwanted overshoot (lower threshold) or to speed up

settling (higher threshold).

Closed-Loop Sequencing

On power-up or following a reset, the system is configured as

follows:

•

The four bipolar outputs (BI-VOUT0 to BI-VOUT3) are set to

their clamp value, regardless of the levels of the SLEEP0 or

the SLEEP1 pin.

•

All of the DAC data registers are set to 0x0000, and the

bipolar DACs operate in open loop.

•

The PA_ON signal is set to the off state.

To enter closed-loop operation, it is important to follow these steps:

1. Configure the AD7293 for closed-loop operating mode by

writing to the integrator limit and closed-loop control register

(Register 0x28) from the configuration page. Additionally,

if PMOS drain switch control is used, set the PA_ON signal

to the on state by writing to the PA_ON control register

(Register 0x29) from the same page.

2. The DACs must be programmed at this point. Choose the

target drain current such that the PA is within its operating

region. The ISENSE gain setting must be left at the default

value of 6.25 in closed-loop mode. At this point, setting the

corresponding ramp time to 0 may be required so that the

ramp generator disables, and the DAC jumps to the target

value quickly.

3. Release the DACs out of clamp by writing to the DAC

enable register (Register 0x04) and wait 5 ms for the PAs to

settle to the initial drain current. At this point, ensure that

the programmed ramp time is 0, such that the ramp generator

is disabled, and the DAC resolves to the target value.

4. Program the desired ramp times for each channel by writing

to the corresponding ramp time registers (Register 0x2A to

5. Program the target drain current by writing to the DAC

registers. In addition to the ramp time, allow a delay of

1 ms before checking whether the PA drain current

corresponds to the intended target current. During the

active ramp period, if the DAC input register (Page 0x00,

ramping up or ramping down to the target code.

If the user writes a new target drain current while the ramp is

active, the device restarts the internal timer and aims to reach

the new drain current within the programmed ramp time.

If the device is configured in closed-loop mode, the ADC runs

conversions on the corresponding current sensor channel in the

background. In addition to the current sensor conversions,

additional channels can be configured to run background

conversions (via the corresponding background enable registers).

The user can read back the conversion results via the channel

specific result registers in Page 0x00 and Page 0x01.

Closed-Loop Integrator Programmable Voltage Limit

The AD7293 ADC can monitor the voltage at the output of the

integrator by writing to a register (Register 0x23) from the

configuration page (see Table 46).

The integrator voltage limit feature allows the user to set upper

and lower limits on the integrator output voltage in closed-loop

mode of operation. When the integrator limit is active, the

integrator pauses and the output voltage holds constant. The

polarity of the error amplifier (comparison between measured

current and target current) determines when it is safe to deactivate

the soft limit. For example, a lower target current is programmed,

which makes the integrator output decrease, making it safe to

deactivate the integrator limit.

It is recommended to use the hysteresis registers (see Table 66

and Table 69) to avoid the device switching in and out of the

alert condition close to the limits. Additionally, the integrator

limit feature can be made a function of the upper/lower limits

only by ignoring the polarity of the error amplifier (via D2 of

the general register (Register 0x14) from the configuration page).

The integrator limit feature does not enable by default and can

be enabled by writing to the integrator limit and closed-loop

control register (Register 0x28).

RAMP TIME

SETTLING

TIME

DAC RAMP

RS VOLTAGE

AD7293BCPZ Datasheet(PDF) 27 Page - Analog Devices

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