Data Sheet

AD9278

Rev. A | Page 7 of 44

SWITCHING SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, full temperature, unless otherwise noted.

Table 3.

Parameter1

Temperature

Min

Typ

Max

Unit

CLOCK2

Clock Rate

25 MSPS (Mode II)

Full

18.5

25

MHz

40 MSPS (Mode I)

Full

18.5

40

MHz

50 MSPS (Mode III)

Full

18.5

50

MHz

65 MSPS (Mode IV)

Full

18.5

65

MHz

Full

4.8

ns

Full

4.8

ns

OUTPUT PARAMETERS2, 3

Full

ns

Full

300

ps

Full

300

ps

Full

ns

Full

ns

Full

ps

Full

ps

Full

±100

±350

ps

Wake-Up Time (Standby), GAIN+ = 0.5 V

25°C

2

µs

Wake-Up Time (Power-Down)

25°C

1

ms

Pipeline Latency

Full

8

Clock

cycles

APERTURE

Aperture Uncertainty (Jitter)

25°C

<1

ps rms

LO GENERATION

4LO Frequency

Full

4

40

MHz

LO Divider RESET Setup Time5

Full

5

ns

LO Divider RESET Hold Time5

Full

5

ns

LO Divider RESET High Pulse Width

Full

20

ns

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were

completed.

2

Can be adjusted via the SPI.

3

Measurements were made using a part soldered to FR-4 material.

4

5

RESET edge to rising 4LO edge.