AD9671KBCZ datasheet(28/61 Pages) AD

28 / 61 page

Data Sheet

AD9671

Rev. A| Page 27 of 60

Address

0x00F,

Bits[7:3]

LPF Cutoff

Frequency (MHz)

Sampling Frequency (MHz)

20.5

125

1 0000

1.45 × (1/6) × fSAMPLE

Out of tunable

filter range

Out of tunable

filter range

15.71

19.33

Out of tunable filter

range

1 0001

1.25 × (1/6) × fSAMPLE

Out of tunable

filter range

Out of tunable

filter range

13.54

16.67

26.04

1 0010

1.13 × (1/6) × fSAMPLE

Out of tunable

filter range

Out of tunable

filter range

Out of tunable filter

range

15.00

23.44

1 0011

1.0 × (1/6) × fSAMPLE

Out of tunable

filter range

Out of tunable

filter range

Out of tunable filter

range

Out of tunable filter

range

20.83

1 0100

0.9 × (1/6) × fSAMPLE

Out of tunable filter

range

Out of tunable filter

range

Out of tunable filter

range

Out of tunable filter

range

18.75

1 0101

0.8 × (1/6) × fSAMPLE

Out of tunable filter

range

Out of tunable filter

range

Out of tunable filter

range

Out of tunable filter

range

16.67

1 0110

0.75 × (1/6) × fSAMPLE

Out of tunable filter

range

Out of tunable filter

range

Out of tunable filter

range

Out of tunable filter

range

15.63

Table 13. High-Pass Filter Cutoff Options

Address 0x02B[1:0] High-Pass Filter Cutoff

High-Pass Cutoff Frequency

Ratio1

Low-Pass Cutoff = 8 MHz

Low-Pass Cutoff = 18 MHz

00 (default)

12.00

670 kHz

1.5 MHz

9.00

890 kHz

2.0 MHz

6.00

1.33 MHz

3.0 MHz

3.00

2.67 MHz

6.0 MHz

1 Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency.

AAF/VGA Test Mode

For debug and testing, there is a bypass switch to view the AAF

output on the GPO2 and GPO3 pins. Enable this mode via SPI

Address 0x109, Bit 4. The differential AAF output of only one

channel can be accessed at a time. The dc output voltage is 1.5 V

(or AVDD2/2) and the maximum ac output voltage is 2 V p-p.

ADC

The AD9671 uses a pipelined ADC architecture. The quantized

output from each stage is combined into a 14-bit result in the

digital correction logic. The pipelined architecture permits the

first stage to operate on a new input sample and the remaining

stages to operate on preceding samples. Sampling occurs on the

rising edge of the clock.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and output clocks.

Clock Input Considerations

For optimum performance, clock the AD9671 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled into the CLK+ and CLK− pins via a

transformer or capacitors. These pins are biased internally and

require no additional bias.

Figure 39 shows the preferred method for clocking the AD9671.

A low jitter clock source, such as the Valpey Fisher oscillator,

VFAC3AHL-1 80.000, is converted from single-ended to

differential using an RF transformer. The back to back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9671 to approximately 0.8 V p-p differential. This

limit prevents the large voltage swings of the clock from feeding

through to other portions of the AD9671, and it preserves the

fast rise and fall times of the signal, which are critical to low

jitter performance.

0.1µF

SCHOTTKY

DIODES:

HSM2812

3.3V

50Ω

100Ω

CLK–

CLK+

ADC

MINI-CIRCUITS®

ADT1-1WT, 1:1Z

XFMR

VFAC3

OUT

Figure 39. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac couple a

differential positive emitter-coupled logic (PECL) signal to the

sample clock input pins, as shown in Figure 40. Analog Devices,

Inc., offers a family of clock drivers with excellent jitter perform-

ance, including the AD9516-0, AD9516-1, AD9516-2, AD9516-3,

and AD9516-5 (these five devices are represented by AD9516-x in

Figure 40, Figure 41, and Figure 42), as well as the AD9524.

100Ω

0.1µF

240Ω

AD9516-x OR AD9524

CLK

*50Ω RESISTOR IS OPTIONAL.

PECL DRIVER

3.3V

OUT

VFAC3

CLK–

CLK+

ADC

50Ω*

Figure 40. Differential PECL Sample Clock

AD9671KBCZ Datasheet(PDF) 28 Page - Analog Devices

AD9671KBCZ Datasheet(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL