AD9671KBCZ datasheet(11/61 Pages) AD

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AD9671

Data Sheet

Rev. A| Page 10 of 60

Parameter1

Temperature

Min

Typ

Max

Unit

Data Rate per Lane

25°C

5.0

Gbps

Uncorrelated Bounded High Probability (UBHP) Jitter

25°C

Random Jitter at 2.5 Gbps Data Rate

25°C

ps rms

Random Jitter at 5 Gbps Data Rate

25°C

ps rms

Output Rise/Fall Time

25°C

TERMINATION CHARACTERISTICS

Differential Termination Resistance

Full

100

APERTURE

Aperture Uncertainty (Jitter)

25°C

ps rms

LO GENERATION

MLO± Frequency

4LO Mode

Full

MHz

8LO Mode

Full

MHz

16LO Mode

Full

160

MHz

RESET± to MLO± Setup Time (tSETUP)

Full

tMLO7/2

RESET± to MLO± Hold Time (tHOLD)

Full

tMLO7/2

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were

completed.

2 Can be adjusted via the SPI.

3 Mode III must have the RF decimator enabled.

4 Mode IV must have the RF decimator enabled.

5 PLL lock time from 0 Hz to 40 MHz frequency change.

6 Wake-up time is defined as the time required to return to normal operation from power-down mode.

7 The period of the MLO clock signal is represented by tMLO.

CLK±, TX_TRIG± Synchronization Timing Diagram

CLK–

CLK+

TX_TRIG+

TX_TRIG–

tEH

tEL

tSETUP

tHOLD

Figure 2. TX_TRIG± to CLK± Input Timing

CW Timing Diagram

MLO–

MLO+

RESET–

RESET+

tMLO

tSETUP

tHOLD

Figure 3. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 4LO Mode

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