ADUCM310 datasheet(5/28 Pages) AD

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ADuCM310

Data Sheet

Rev. B Page 4 of 27

SPECIFICATIONS

AVDD = IOVDD = DVDD = 2.9 V to 3.6 V (the input supply voltages). The difference between AVDD, IOVDD, and DVDD must be ≤0.3 V.

AVNEG (the supply voltage) = −5.5 V to −4.65 V. VDACVDD (the VDAC supply voltage) = 3.07 V to 5.35 V (for VDAC6 and VDAC7),

and VDACVDD must be ≥ AVDD. PVDD (the IDAC supply voltage) for the IDACs = 1.8 V to 2.7 V. AVDD ≥ PVDD + 0.4V. VREF= 2.5 V

internal reference, fCORE = 80 MHz, TA = −40°C to +85°C, unless otherwise noted.

For power sequencing, connect the AGND, DGND, PGND, and IOGND pins to ground before applying power to the AVNEGor VDACVDDpins.

For register and bit information, see the ADuCM310 reference manual, How to Set Up and Use the ADuCM310.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

All measurements in single-ended

mode, unless otherwise stated

ADC Power-Up Time

µs

fSAMPLE ≥500 kSPS

DC Accuracy

Resolution

Bits

Integral Nonlinearity

Input Buffer

Disabled

±2

LSB

2.5 V internal reference

±1.51

LSB

2.5 V internal reference

Enabled

±2.5

LSB

Disabled

±2

LSB

External reference

±1.51

LSB

External reference

Differential Nonlinearity

−0.99

±0.7

+1.51

LSB

2.5 V external reference;

no missing codes

−0.99

±0.7

+2.0

LSB

2.5 V external reference;

no missing codes

DC Code Distribution

±3

LSB

ADC input voltage = 1.25 V dc

±5

ENDPOINT ERRORS

Offset Error (All Channels Except

the Internal Channels)

ADC update rate up to 800 kSPS

Buffer On or Buffer Off

−0.8

±0.2

+0.8

Buffer on, chop mode on and

automatic zero or buffer off

−0.61

±0.2

+0.61

Buffer on, chop mode on and

automatic zero or buffer off

Offset Error Drift2

Buffer On or Buffer Off

±3.2

µV/°C

Buffer on, chop mode on and

automatic zero or buffer off

±2.51

µV/°C

Buffer on, chop mode on and

automatic zero or buffer off

Full-Scale Error

ADC update rate up to 800 kSPS

Buffer On or Buffer Off

−0.75

±0.2

+0.75

Excluding internal channels

−0.71

±0.2

+0.61

Excluding internal channels

Internal Channels

±0.2

% of full scale

Input buffer on; AVDD/2, IOVDD/2,

PVDD voltage on PVDD_IDAC2 pin

±0.2

±0.61

% of full scale

Input buffer on; AVDD/2, IOVDD/2,

PVDD voltage on PVDD_IDAC2 pin

0.75

% of full scale

Input buffer on; IDAC0 to IDAC5;

measured with 1.5 V on the IDAC0

to IDAC5 pins

0.75

1.51

% of full scale

Input buffer on; IDAC0 to IDAC5;

measured with 1.5 V on the IDAC0

to IDAC5 pins

Gain Error Drift2

µV/°C

Full-scale error drift minus offset

error drift; all modes; internal

reference

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