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ADUCM310 Datasheet(PDF) 14 Page - Analog Devices |
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ADUCM310 Datasheet(HTML) 14 Page - Analog Devices |
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14 / 28 page ![]() Data Sheet ADuCM310 Rev. B Page 13 of 27 SDAx (I/O) tBUF MSB LSB ACK MSB 1 9 8 2 TO 7 1 SCLx (I) P S S(R) REPEATED START START CONDITION STOP CONDITION tR tF tF tR tH tVD;DAT tL tDSU tDHD tRSU tDHD tDSU tSHD tPSU tVD;ACK Figure 2. I2C Compatible Interface Timing SPI Timing Table 4. SPI Master Mode Timing (Phase Mode = 1) Parameter Description Min Typ Max Unit tSL SCLKx low pulse width (SPIxDIV1 + 1) × tHCLK2/2 ns tSH SCLKx high pulse width (SPIxDIV1 + 1) × tHCLK2/2 ns tDAV Data output valid after SCLKx edge 0 3 ns tDSU Data input setup time before SCLKx edge ½ SCLKx ns tDHD Data input hold time after SCLKx edge SCLKx ns tDF Data output fall time SCLKx ns tDR Data output rise time 25 ns tSR SCLKx rise time 25 ns tSF SCLKx fall time 20 ns 1 For SPI0, x is 0, and for SPI1, x is 1. 2 tHCLK is the divided system clock, UCLK/CLKCON1[2:0]. SCLKx (POLARITY = 0) SCLKx (POLARITY = 1) MOSIx MSB BIT 6 TO BIT 1 LSB MISOx MSB IN BIT 6 TO BIT 1 LSB IN tSH tSL tSR tSF tDR tDF tDAV tDSU tDHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) |
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