HT32F22366 datasheet(42/56 Pages) HOLTEK

42 / 56 page

Rev. 1.00

4� of 56

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3�-Bit A��® Co�tex®-M3 MCU

HT3�F1�365/HT3�F1�366/HT3�F��366

SAR ADC

sa�ple

Figure 8. ADC Sampling Network Model

The worst case occurs when the extremities of the input range (0 V and VREF) are sampled

consecutively. In this situation a sampling error below 1/4 LSB is ensured by using the following

equation:

RS <

fADCCIln(2N+2)

3.5

– RI

Where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe

margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for

in this simple model.

If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations

between consecutive sampling phases, RS may be larger than the value indicated by the equation

above.

Comparator Characteristics

Table 20. Comparator Characteristics

TA = �5 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

VDDA

Ope�ating voltage

Co�pa�ato� �ode

�.5

3.3

3.6

VI�

Input Co��on Mode

Voltage Range

CP o� C�

VSSA

—

VDDA

VIOS

Input offset voltage(1)

TA = �5 °C

-15

—

�V

Vhys

Input Hyste�esis

�o hyste�esis

(CMPnHM[1:0] = 00)

Low Speed

—

�V

High Speed

—

Low hyste�esis

(CMPnHM[1:0] = 01)

Low Speed

—

�V

High Speed

—

Middle hyste�esis

(CMPnHM[1:0] = 10)

Low Speed

—

�V

High Speed

—

�0

—

High hyste�esis

(CMPnHM[1:0] = 11)

Low Speed

—

�0

—

�V

High Speed

—

100

—

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