MB91F467BA datasheet(117/127 Pages) CYPRESS

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MB91460B Series

Document Number: 002-04608 Rev. *A

Page 116 of 126

15.7.7 External Bus AC Timings at VDD35  3.0 to 5.5 V

Note: This chapter is applicable to MB91F467BA/F466BA

■ Conditions during AC measurements

All AC tests were measured under the following conditions:

❐ -IOdrive  5 mA

❐ -VDD35  4.5 V to 5.5 V, Iload  3 mA

❐ -VSS5  0 V

❐ -Ta   40 C to  125 C

❐ -Cl  50 pF

❐ -VOL  0.5 × VDD35

❐ -VOH = 0.5 × VDD35

❐ -EPILR  0, PILR  1 (Automotive Level  worst case)

15.7.7.1

Basic Timing

(VDD35  3.0 V to 5.5 V, Vss5  AVss5  0 V, TA  40 C to  125 C)

Note: tCLKT is the cycle time of the external bus clock.

Parameter

Symbol

Pin name

Value

Unit

Min

Max

SYSCLK

tCLCH

SYSCLK

1/2 x tCLKT - 1

1/2 × tCLKT + 9

tCHCL

1/2 × tCLKT - 9

1/2 × tCLKT + 1

SYSCLK ↓ to CSXn delay time

tCLCSL

SYSCLK

CSXn

-8

tCLCSH

-12

SYSCLK ↑ to CSXn delay time (Addr → CS delay)

tCHCSL

- 6

+ 1

SYSCLK ↓ to Address valid delay time

tCLAV

SYSCLK

A21 to A0

-13

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