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MB95F856K Datasheet(PDF) 38 Page - Cypress Semiconductor |
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MB95F856K Datasheet(HTML) 38 Page - Cypress Semiconductor |
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38 / 172 page  Document Number: 002-09305 Rev. *C Page 38 of 172 PRELIMINARY MB95F856K, MB95F866K, MB95F876K 0x0E54 STRTH4 TS touch strength threshold setting register ch. 4 R/W 0b00000001 0x0E55 STRTH5 TS touch strength threshold setting register ch. 5 R/W 0b00000001 0x0E56 to 0x0E60 — (Disabled) — — 0x0E61 STR1 TS touch strength register ch. 1 R 0bXXXXXXXX 0x0E62 STR2 TS touch strength register ch. 2 R 0bXXXXXXXX 0x0E63 STR3 TS touch strength register ch. 3 R 0bXXXXXXXX 0x0E64 STR4 TS touch strength register ch. 4 R 0bXXXXXXXX 0x0E65 STR5 TS touch strength register ch. 5 R 0bXXXXXXXX 0x0E66 to 0x0E70 — (Disabled) — — 0x0E71 CALIP1 TS calibrated impedance register ch. 1 R 0b0XXXXXXX 0x0E72 CALIP2 TS calibrated impedance register ch. 2 R 0b0XXXXXXX 0x0E73 CALIP3 TS calibrated impedance register ch. 3 R 0b0XXXXXXX 0x0E74 CALIP4 TS calibrated impedance register ch. 4 R 0b0XXXXXXX 0x0E75 CALIP5 TS calibrated impedance register ch. 5 R 0b0XXXXXXX 0x0E76 to 0x0E80 — (Disabled) — — 0x0E81 IMPE1 TS impedance register ch. 1 R 0b0XXXXXXX 0x0E82 IMPE2 TS impedance register ch. 2 R 0b0XXXXXXX 0x0E83 IMPE3 TS impedance register ch. 3 R 0b0XXXXXXX 0x0E84 IMPE4 TS impedance register ch. 4 R 0b0XXXXXXX 0x0E85 IMPE5 TS impedance register ch. 5 R 0b0XXXXXXX 0x0E86 to 0x0E8F — (Disabled) — — 0x0E90 TOUCHL TS touch data register (lower) R 0bXXXXXXXX 0x0E91 TOUCHH TS touch data register (upper) R 0b0000XXXX 0x0E92 INTPR TS interrupt pending register R 0b000XXXXX 0x0E93 to 0x0F7F — (Disabled) — — 0x0F80 WRARH0 Wild register address setting register (upper) ch. 0 R/W 0b00000000 0x0F81 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000 0x0F82 WRDR0 Wild register data setting register ch. 0 R/W 0b00000000 0x0F83 WRARH1 Wild register address setting register (upper) ch. 1 R/W 0b00000000 0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000 0x0F85 WRDR1 Wild register data setting register ch. 1 R/W 0b00000000 0x0F86 WRARH2 Wild register address setting register (upper) ch. 2 R/W 0b00000000 0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000 0x0F88 WRDR2 Wild register data setting register ch. 2 R/W 0b00000000 0x0F89 to 0x0F91 — (Disabled) — — 0x0F92 T01CR0 8/16-bit composite timer 01 status control register 0 R/W 0b00000000 0x0F93 T00CR0 8/16-bit composite timer 00 status control register 0 R/W 0b00000000 0x0F94 T01DR 8/16-bit composite timer 01 data register R/W 0b00000000 0x0F95 T00DR 8/16-bit composite timer 00 data register R/W 0b00000000 0x0F96 TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 0b00000000 0x0F97 to 0x0F9B — (Disabled) — — Address Register abbreviation Register name R/W Initial value |
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