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MB95F856K Datasheet(PDF) 39 Page - Cypress Semiconductor

Part # MB95F856K
Description  The MB95850K/860K/870K Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of these series contain a variety of peripheral functions.
PDF  172 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB95F856K Datasheet(HTML) 39 Page - Cypress Semiconductor

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Document Number: 002-09305 Rev. *C
Page 39 of 172
PRELIMINARY
MB95F856K, MB95F866K,
MB95F876K
■ R/W access symbols
■ Initial value symbols
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
0x0F9C
PPS01
8/16-bit PPG01 cycle setting buffer register
R/W
0b11111111
0x0F9D
PPS00
8/16-bit PPG00 cycle setting buffer register
R/W
0b11111111
0x0F9E
PDS01
8/16-bit PPG01 duty setting buffer register
R/W
0b11111111
0x0F9F
PDS00
8/16-bit PPG00 duty setting buffer register
R/W
0b11111111
0x0FA0 to 0x0FA3
—
(Disabled)
—
—
0x0FA4
PPGS
8/16-bit PPG start register
R/W
0b00000000
0x0FA5
REVC
8/16-bit PPG output inversion register
R/W
0b00000000
0x0FA6 to 0x0FBD
—
(Disabled)
—
—
0x0FBE
PSSR0
UART/SIO dedicated baud rate generator prescaler select
register ch. 0
R/W
0b00000000
0x0FBF
BRSR0
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
R/W
0b00000000
0x0FC0
TIDR0
Touch input disable register 0
R/W
0b00000000
0x0FC1
TIDR1
Touch input disable register 1
R/W
0b00000000
0x0FC2
—
(Disabled)
—
—
0x0FC3
AIDRL
A/D input disable register (lower)
R/W
0b00000000
0x0FC4
LVDPW
LVD reset circuit password register
R/W
0b00000000
0x0FC5 to 0x0FE2
—
(Disabled)
—
—
0x0FE3
WCDR
Watch counter data register
R/W
0b00111111
0x0FE4
CRTH
Main CR clock trimming register (upper)
R/W
0b000XXXXX
0x0FE5
CRTL
Main CR clock trimming register (lower)
R/W
0b000XXXXX
0x0FE6
—
(Disabled)
—
—
0x0FE7
CRTDA
Main CR clock temperature dependent adjustment register
R/W
0b000XXXXX
0x0FE8
SYSC
System configuration register
R/W
0b11000011
0x0FE9
CMCR
Clock monitoring control register
R/W
0b00000000
0x0FEA
CMDR
Clock monitoring data register
R
0b00000000
0x0FEB
WDTH
Watchdog timer selection ID register (upper)
R
0bXXXXXXXX
0x0FEC
WDTL
Watchdog timer selection ID register (lower)
R
0bXXXXXXXX
0x0FED, 0x0FEE
—
(Disabled)
—
—
0x0FEF
WICR
Interrupt pin selection circuit control register
R/W
0b01000000
0x0FF0 to 0x0FFF
—
(Disabled)
—
—
R/W
: Readable/Writable
R
: Read only
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Address
Register
abbreviation
Register name
R/W
Initial value



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