COP404C datasheet(6/18 Pages) NSC

6 / 18 page

Functional Description

INTERNAL LOGIC

The processor contains its own 4-bit A register (accumula-

tor) which is the source and destination register for most

IO arithmetic logic and data memory access operations

It can also be used to load the Br and Bd portions of the B

counter L IO ports data to input 4-bit G or IN ports and to

perform data exchanges with the SIO register

A 4-bit adder performs the arithmetic and logic functions

storing the results in A It also outputs a carry bit to the 1-bit

C register most often employed to indicate arithmetic over-

flow The C register in conjunction with the XAS instruction

and the EN register also serves to control the SK output

The 8-bit T counter is a binary up counter which can be

loaded to and from M and A using CAMT and CTMA instruc-

tions This counter is operated as a time-base counter

When the T counter overflows an overflow flag will be set

(see SKT and IT instructions below) The T counter is

cleared on reset A functional block diagram of the timer

counter is illustrated in

Figure 10a

Four general-purpose inputs IN3 – IN0 are provided IN1

IN2 and IN3 may be selected (by pulling MB pin low) as

Read Strobe Chip Select and Write Strobe inputs respec-

tively for use in MICROBUS application

The D register provides 4 general-purpose outputs and is

used as the destination register for the 4-bit contents of Bd

In the dual clock mode D0 latch controls the clock selection

(see dual oscillator below)

The G register contents are outputs to a 4-bit general-pur-

pose bidirectional IO port G0 may be selected as an out-

put for MICROBUS applications

The Q register is an internal latched 8-bit register used to

hold data loaded to or from M and A as well as 8-bit data

from ROM Its contents are outputted to the L IO ports

when the L drivers are enabled under program control With

the MICROBUS option selected Q can also be loaded with

the 8-bit contents of the L IO ports upon the occurrence of

a write strobe from the host CPU

The 8 L drivers when enabled output the contents of

latched Q data to the L IO port Also the contents of L may

be read directly into A and M As explained above the MI-

CROBUS option allows L IO port data to be latched into

the Q register

The SIO register functions as a 4-bit serial-inserial-out shift

as a binary counter (depending on the contents of the EN

The XAS instruction copies C into the SKL latch In the

counter mode SK is the output SKL in the shift register

mode SK outputs SKL ANDed with the clock

EN is an internal 4-bit register loaded by the LEI instruction

The state of each bit of this register selects or deselects the

particular feature associated with each bit of the EN regis-

ter

0 The least significant bit of the enable register EN0 se-

lects the SIO register as either a 4-bit shift register or a 4-

bit binary counter With EN0 set SIO is an asynchronous

binary counter decrementing its value by one upon each

low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI input

Each pulse must be at least two instruction cycles wide

SK outputs the value of SKL The SO output equals the

value of EN3 With EN0 reset SIO is a serial shift register

left shifting 1 bit each instruction cycle time The data

present at SI goes into the least significant bit of SIO SO

can be enabled to output the most significant bit of SIO

each cycle time The SK outputs SKL ANDed with the

instruction cycle clock

1 With EN1 set interrupt is enabled Immediately following

an interrupt EN1 is reset to disable further interrupts

2 With EN2 set the L drivers are enabled to output the data

in Q to the L IO port Resetting EN2 disables the L driv-

ers placing the L IO port in a high-impedance input

state

3 EN3 in conjunction with EN0 affects the SO output With

EN0 set (binary counter option selected) SO will output

the value loaded into EN3 With EN0 reset (serial shift

output of the SIO shift register outputting serial shifted

data each instruction time Resetting EN3 with the serial

shift register option selected disables SO as the shift reg-

ister output data continues to be shifted through SIO and

can be exchanged with A via an XAS instruction but SO

remains set to ‘‘0’’

INTERRUPT

The following features are associated with interrupt proce-

dure and protocol and must be considered by the program-

mer when utilizing interrupts

a The interrupt

once recognized as explained below

pushes the next sequential program counter address

(PCa1) onto the stack Any previous contents at the bot-

tom of the stack are lost The program counter is set to

hex address 0FF (the last word of page 3) and EN1 is

reset

b An interrupt will be recognized only on the following con-

ditions

1 EN1 has been set

2 A low-going pulse (‘‘1’’ to ‘‘0’’) at least two instruction

cycles wide has occurred on the IN1 input

3 A currently executing instruction has been completed

TABLE I ENABLE REGISTER MODES

BITS EN0 AND EN3

EN0

EN3

SIO

Shift Register

Input to Shift

If SKLe

SKeclock

If SKLe

SKe

Shift Register

Input to Shift

Serial

If SKLe

SKeclock

out

If SKLe

SKe

Binary Counter

Input to Counter

SK e SKL

Binary Counter

Input to Counter

SK e SKL

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