COP404C datasheet(14/18 Pages) NSC

14 / 18 page

Description of Selected Instructions (Continued)

SKT INSTRUCTION

The SKT (Skip On Timer) instruction tests the state of the T

counter overflow latch (see internal logic above) executing

the next program instruction if the latch is not set If the

latch has been set since the previous test the next program

instruction is skipped and the latch is reset The features

associated with this instruction allow the processor to gen-

erate its own time-base for real-time processing rather than

relying on an external input signal

Note If the most significant bit of the T counter is a 1 when

a CAMT instruction loads the counter the overflow flag will

be set The following sample of codes should be used when

loading the counter

CAMT

load T counter

SKT

skip if overflow flag is set and reset it

NOP

IT INSTRUCTION

The IT (idle till timer) instruction halts the processor and

puts it in an idle state until the time-base counter overflows

This idle state reduces current drain since all logic (except

the oscillator and time base counter) is stopped

INIL INSTRUCTION

INIL (Input IL Latches to A) inputs 2 latches IL3 and IL0

CKOI and 0 into A The IL3 and IL0 latches are set if a low-

going pulse (‘‘1’’ to ‘‘0’’) has occurred on the IN3 and IN0

inputs since the last INIL instruction provided the input

pulse stays low for at least two instruction cycles Execution

of an INIL inputs IL3 and IL0 into A3 and A0 respectively

and resets these latches to allow them to respond to subse-

quent low-going pulses on the IN3 and IN0 lines The state

of CKOI is input into A2 A0is input into A1 IL latches are

cleared on reset

Instruction Set Notes

a The first word of a program (ROM address 0) must be a

CLRA (Clear A) instruction

b Although skipped instructions are not executed they are

still fetched from the program memory Thus program

paths take the same number of cycles whether instruc-

tions are skipped or executed except for JID and LQID

c The ROM is organized into pages of 64 words each The

Program Counter is a 11-bit binary counter and will count

through page boundaries If a JP JSRP JID or LQID is

the last word of a page it operates as if it were in the next

page For example a JP located in the last word of a

page will jump to a location in the next page Also a JID

or LQID located in the last word of every fourth page (ie

hex address 0FF 1FF 2FF 3FF 4FF etc) will access

data in the next group of four pages

Power Dissipation

The lowest power drain is when the clock is stopped As the

frequency increases so does current Current is also lower

at lower operating voltages Therefore for minimum power

dissipation the user should run at the lowest speed and

voltage that his application will allow The user should take

care that all pins swing to full supply levels to insure that

outputs are not loaded down and that inputs are not at

some intermediate level which may draw current Any input

with a slow rise or fall time will draw additional current For

example an RC oscillator on D0 will draw more current than

a square wave clock input since it is a slow rising signal

If using an external square wave oscillator the following

equation can be used to calculate the COP404C operating

current drain

IcoeIq a V c 40 c Fi a V c 1400 c Fi

where

Ico e chip operating current drain in microamps

Iqe quiescent leakage current (from curve)

Fie CKI frequency in MegaHertz

Ve chip VCC in volts

For example at 5 volts VCC and 400 kHz

Icoe20 a 5 c 40 c 4 a 5 c 1400 c 44

Icoe 20 a 80 a 700 e 800 mA

at 24 volts VCC and 30 kHz

Icoe 6 a 24 c 40 c 03 a 24 c 1400 c 0

Icoe 6 a 288 a 252 e 3408 mA

If an IT instruction is executed the chip goes into the IDLE

mode until the timer overflows In IDLE mode the current

drain can be calculated from the following equation

Icie Iq a V c 40 c Fi

For example at 5 volts VCC and 400 kHz

Icie 20 a5 c 40 c 4 e 100 mA

The total average current will then be the weighted average

of the operating current and the idle current

ItaeIcoc

ToaTi

Ici c

ToaTi

where

Itae total average current

Icoe operating current

Icie idle current

Toe operating time

Tie idle time

IO OPTIONS

COP404C outputs have the following configurations illus-

trated in

Figure 12

a Standard

A CMOS push-pull buffer with an N-channel

device to ground in conjunction with a P-channel device

to VCC compatible with CMOS and LSTTL (Used on SO

SK ADDATA SKIP A108 and D outputs)

b Low Current

This is the same configuration as a

above except that the sourcing current is much less

(Used on G outputs)

c Standard TRI-STATE L Output

A CMOS output buffer

similar to a which may be disabled by program control

(Used on L outputs)

All inputs have the following configuration

d Input with on chip load device to VCC (Used on CKOI)

e HI-Z input which must be driven by the users logic (Used

on CKI RESET IN SI DUAL MB SEL10 and SEL20

inputs)

All output drivers use one or more of three common devices

numbered 1 to 3 Minimum and maximum current (IOUT and

VOUT) curves are given in Figure 13 for each of these devic-

es to allow the designer to effectively use these IO configu-

rations

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