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LTC4258

4258p

The START and STOP Conditions

When the bus is idle, both SCL and SDA must be high. A

bus master (typically the host controller) signals the

beginning of communication with a slave device (like the

LTC4258) by transmitting a START condition. A START

condition is generated by transitioning SDA from high to

low while SCL is high. When the master has finished

communicating with the slave, it issues a STOP condition.

A STOP condition is generated by transitioning SDA from

low to high while SCL is high. The bus is then free for

communication with another SMBus or I2C device.

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the latest

byte of information was received. The corresponding SCL

clock pulse is always generated by the master. The master

releases the SDA line (HIGH) during the Acknowledge

clock pulse. The slave must pull down the SDA line during

the Acknowledge clock pulse so that it remains a stable

LOW during the HIGH period of this clock pulse. When the

master is reading from a slave device, it is the master’s

responsibility to acknowledge receipt of the data byte in

the bit that follows unless the transaction is complete. In

that case the master will decline to acknowledge and issue

the STOP condition to terminate the communication.

Write Byte Protocol

The master initiates communication to the LTC4258 with

a START condition and a 7-bit bus address followed by the

Write Bit (Wr) = 0. If the LTC4258 recognizes its own

address, it acknowledges and the master delivers the com-

mand byte, signifying to which internal LTC4258 register

the master wishes to write. The LTC4258 acknowledges

and latches the lower five bits of the command byte into its

command byte are checked by the LTC4258; the upper

three bits are ignored. The master then delivers the data

byte. The LTC4258 acknowledges once more and latches

the data into the appropriate control register. Finally, the

master terminates the communication with a STOP condi-

tion. Upon reception of the STOP condition, the Register

Address register is cleared (see Figure 6).

Read Byte Protocol

The master initiates communication from the LTC4258

with a START condition and the same 7-bit bus address

followed by the Write Bit (Wr) = 0. If the LTC4258

recognizes its own address, it acknowledges and the

master delivers the command byte, signifying which

internal LTC4258 register it wishes to read from. The

LTC4258 acknowledges and latches the lower five bits of

the command byte into its Register Address register. At

this time the master sends a REPEATED START condition

and the same 7-bit bus address followed by the Read Bit

(Rd) = 1. The LTC4258 acknowledges and sends the

contents of the requested register. Finally, the master

declines to acknowledge and terminates communication

with a STOP condition. Upon reception of the STOP

condition, the Register Address register is cleared (see

Figure 7).

Receive Byte Protocol

Since the LTC4258 clears the Register Address register on

each STOP condition, the interrupt register (register 0)

may be read with the Receive Byte Protocol as well as with

the Read Byte Protocol. In this protocol, the master

initiates communication with the LTC4258 with a START

condition and a 7-bit bus address followed by the Read Bit

(Rd) = 1. The LTC4258 acknowledges and sends the

contents of the interrupt register. The master then de-

clines to acknowledge and terminates communication

with a STOP condition (see Figure 8).

Alert Response Address and the INT Pin

In a system where several LTC4258s share a common INT

line, the master can use the Alert Response Address (ARA)

to determine which LTC4258 initiated the interrupt.

The master initiates the ARA procedure with a START

condition and the 7-bit ARA bus address (0001100)b

followed by the Read Bit (Rd) = 1. If an LTC4258 is

asserting the INT pin, it acknowledges and sends its 7-bit

bus address (010A3A2A1A0)b and a 1 (see Figure 9). While

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