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LTM4653

Rev 0

For more information www.analog.com

PIN FUNCTIONS

VIN (A1-A3, B3): Power Input Pins. Apply input voltage

and input decoupling capacitance directly between VIN

and a ground (PGND) plane.

VD (A4, B4, C4): Drain of the Converter’s Primary Switch-

ing MOSFET. Apply at minimum one 4.7µF high frequency

ceramic decoupling capacitor directly from VD to PGND.

Give this capacitor higher layout priority (closer proximity

to the module) than any VIN decoupling capacitors.

SVIN (C3): Input Voltage Supply for Small-Signal Circuits.

SVIN is the input to the INTVCC LDO. Connect SVIN directly

to VIN. No decoupling capacitor is needed on this pin.

PGND (A5, B5, C5, D5, E5, F5, G4-5, H3, H5, J3-5, K4-

5, L4-5): Power Ground Pins of the LTM4653. Connect

all pins to the application’s PGND plane.

VOUT (K1-3, L1-3): Power Output Pins of the LTM4653.

Connectallpinstotheapplication’spowerVOUTplane.Apply

the output filter capacitors and the output load between

a power VOUT plane and the application’s PGND plane.

GND (D4): Ground Pin of the LTM4653. Electrically con-

nect to the application’s PGND plane.

VOSNS(G1,H1):OutputVoltageSenseandFeedbackSignal.

Connect VOSNS to VOUT at the point of load (POL). Pins G1

and H1 are electrically connected to each other internal to

the module, and thus it is only necessary to connect one

VOSNS pin to VOUT at the POL. The remaining VOSNS pin

can be used for redundant connectivity or routed to an ICT

test point for design-for-test considerations, as desired.

SGND (E4, G2, H2): Signal Ground Pins of the LTM4653.

Connect Pin H2 to PGND directly under the LTM4653. The

SGND pins at locations E4 and G2 are electrically con-

nected to each other internal to the module, and thus it is

only necessary to connect one SGND pin to PGND under

the module. The remaining SGND pins can be used for

redundant connectivity or routed to an ICT test point for

design-for-test considerations, as desired.

RUN (F4): Run Control Pin. A voltage above 1.2V com-

mands the Module to regulate its output voltage. Under-

voltagelockout(UVLO)canbeimplementedbyconnecting

RUN to the midpoint node formed by a resistor-divider

between VIN and GND. RUN features 130mV of hysteresis.

See the Applications Information section.

INTVCC (G3): Internal Regulator, 3.3V Nominal Output.

Internal control circuits and MOSFET-drivers derive pow-

er from INTVCC bias. When operating 3.1V < SVIN ≤ 58V,

an LDO generates INTVCC from SVIN when RUN is logic

high (RUN > 1.2V). No external decoupling is required.

When RUN is logic low (RUN - GND < 1.2V), the INTVCC

LDO is off, i.e., INTVCC is unregulated. (Also see EXTVCC.)

EXTVCC (F3): External Bias, Auxiliary Input to the INTVCC

Regulator. When EXTVCC exceeds 3.2V and SVIN exceeds

5V, the INTVCC LDO derives power from EXTVCC bias

instead of the SVIN path. This technique can reduce LDO

losses considerably, resulting in a corresponding reduc-

tion in module junction temperature. For applications in

which 4V ≤ VOUT≤26.5V,connectEXTVCCtoVOUTthrough

a resistor. (See the Applications Information section for

resistor value.) When taking advantage of this EXTVCC

feature, locally decouple EXTVCC to PGND with a 1µF ce-

ramic—otherwise, leave EXTVCC open circuit.

ISETb (F1): 1.5nF Soft-Start Capacitor. Connect ISETb

to ISETa to achieve default soft-start characteristics, if

desired. See ISETa.

ISETa (F2): Accurate 50μA Current Source. Positive input

to the error amplifier. Connect a resistor (RISET) from this

pin to SGND to program the desired LTM4653 output volt-

age, VOUT = RISET • 50μA. A capacitor can be connected

from ISETa to SGND to soft-start the output voltage and

reduce start-up inrush current. Connect ISETa to ISETb in

order to achieve default soft-start, if desired. (See ISETb.)

In addition, the output of the LTM4653 can track a voltage

applied between the ISETa pin and the SGND pins. (See

the Applications Information section.)

PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

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