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LTM8049 Datasheet(PDF) 26 Page - Linear Technology

Part # LTM8049
Description  EN55022B Compliant 58V, 4A Step-Down DC/DC 關Module Regulator
PDF  32 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTM8049 Datasheet(HTML) 26 Page - Linear Technology

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LTM4653
26
Rev 0
For more information www.analog.com
Figure 26. 24V to 15VOUT Derating
Curve, with BGA Heat Sink
Figure 27. 48V to 15VOUT Derating
Curve, with BGA Heat Sink
Figure 28. 48V to 24VOUT Derating
Curve, with BGA Heat Sink
APPLICATIONS INFORMATION—DERATING CURVES
APPLICATIONS INFORMATION
Safety Considerations
The LTM4653 does not provide galvanic isolation from VIN
to VOUT. There is no internal fuse. If required, a slow blow
fuse with a rating twice the maximum input current needs
to be provided to protect the unit from catastrophic failure.
The fuse or circuit breaker, if used, should be selected to
limit the current to the regulator in case of a MT MOSFET
fault. If MT fails, the system’s input supply will source
very large currents to VOUT through MT. This can cause
excessive heat and board damage depending on how
much power the input voltage can deliver to this system.
A fuse or circuit breaker can be used as a secondary fault
protector in this situation. The LTM4653 does feature
overcurrent and overtemperature protection.
Layout Checklist/Example
The high integration of LTM4653 makes the PCB board
layout straightforward. However, to optimize its electrical
and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, PGND and VOUT. Doing so helps to
minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output ca-
pacitors next to the VIN, VD, PGND and VOUT pins to
minimize high frequency noise.
• Place a dedicated power ground layer underneath the
LTM4653.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on pads, unless they are capped
or plated over.
• Use a separate SGND copper plane for components
connected to signal pins. Connect SGND to PGND
directly under the module.
• For parallel module applications, connect the VOUT,
VOSNS, RUN, ISETa, COMPa and PGOOD pins together
as shown in Figure 32.
• Bring out test points on the signal pins for monitoring.
Figure  29 gives a good example of the recommended
LTM4653 layout.
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
4653 F26
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
400LFM
200LFM
OLFM
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
4653 F27
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
400LFM
200LFM
OLFM
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
4653 F28
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
400LFM
200LFM
OLFM
See Table 1 for fSW and REXTVCC.



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