HSP50214BVCZ datasheet(30/62 Pages) RENESAS

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HSP50214B

FN4450 Rev 4.00

Page 30 of 62

May 1, 2007

Cartesian to Polar Converter

The Cartesian to Polar converter computes the magnitude

and phase of the I/Q vector. The I and Q inputs are 18 bits.

The converter phase output is 18-bits (truncated) with the 16

MSB’s routed to the output formatter and all 18-bits routed to

the frequency discriminator. The 16-bit output phase can be

interpreted either as two’s complement (-0.5 to

approximately 0.5) or unsigned (0.0 to approximately 1.0),

as shown in Figure 28. The phase conversion gain is 1/2

.

The phase resolution is 16-bits. The 16-bit magnitude is

unsigned binary format with a range from 0 to 2.32. The

magnitude conversion gain is 1.64676. The magnitude

resolution is 16 bits. The MSB is always zero.

Table 11 details the phase and magnitude weighting for the

16-bits output from the PDC.

The magnitude and phase computation requires 17 clocks

for full precision. At the end of the 17 clocks, the magnitude

and phase are latched into a register to be held for the next

stage, either the output formatter or frequency discriminator.

If a new input sample arrives before the end of the 17 cycles,

the results of the computations up until that time, are

latched. This latching means that an increase in speed

causes only a decrease in resolution. Table 12 details the

exact resolution that can be obtained with a fixed number of

clock cycles up to the required 17. The input magnitude and

phase errors induced by normal SNR values will almost

always be worse than the Cartesian to Polar conversion.

In the HSP50214, the input to the coordinate converter I/Q to

|r|/

 block is 18-bits. If the signal range is large and the AGC

is not used, the quantization noise can become a

contributing factor in the phase and frequency computations.

For example, if the signal range is 84dB and the maximum

signal is set at full scale, the minimum signal would have

only 4-bits each for I and Q.

In the HSP50214B, an additional data path option was

added that allows the output of the 255 tap programmable

FIR filter to be routed directly to the coordinate converter.

Rather than having to select only 18-bits out of the available

26 bit output, all 26-bits of the FIR output are routed to the

coordinate converter. This change eliminates quantization

effects to give more accuracy in the phase and frequency

discriminator outputs. The AGC settling time is not a factor

because the AGC is effectively bypassed for the magnitude,

phase, and frequency computations.

NOTE: The most significant 18-bits of the computed phase are

still routed to the discriminator.

TABLE 11. MAG/PHASE BIT WEIGHTING

BIT

MAGNITUDE

PHASE (o)

15 (MSB)

22 (Always 0)

180

2-1

22.5

2-2

11.25

2-3

5.625

2-4

2.8125

2-5

1.40625

2-6

0.703125

2-7

0.3515625

2-8

0.17578125

2-9

0.087890625

2-10

0.043945312

2-11

0.021972656

2-12

0.010986328

0 (LSB)

2-13

0.005483164

+/2



-/2

/2



/2

0000

7fff

ffff

3ff f

c000

0000

8000

4000

bfff

ffff

3fff

4000

7fff

8000

c000

bfff

FIGURE 28. PHASE BIT MAPPING OF COORDINATE

CONVERTER OUTPUT

TABLE 12. MAG/PHASE ACCURACY vs CLOCK CYCLES

CLOCKS

MAGNITUDE

ERROR

(% fS)

PHASE

ERROR

(DEG.)

†

PHASE

ERROR

(% fS)

0.065

3.5

0.016

1.8

0.004

0.9

0.5

<0.004

0.45

0.25

<0.004

0.22

0.12

<0.004

0.11

0.062

<0.004

0.056

0.03

<0.004

0.028

0.016

<0.004

0.014

0.008

<0.004

0.007

0.004

<0.004

0.0035

0.002

<0.004

0.00175

0.001

† Assumes 180o = fS.

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