HSP50214BVCZ datasheet(14/62 Pages) RENESAS

14 / 62 page

HSP50214B

FN4450 Rev 4.00

Page 14 of 62

May 1, 2007

The phase of the Carrier NCO can be shifted by adding a 10-

bit phase offset to the MSB’s (modulo 360o) of the output of

the phase accumulator. This phase offset control has a

resolution of 0.35o and can be interpreted as two’s

complement from -180o to 180o

(-to) or as binary from 0

to 360o

(0to2). The phase offset is given by:

or, in terms of the parameter to be programmed:

where PO is the 10-bit two’s complement value loaded into the

Phase Offset Register (Control Word 4, Bits 9-0). For example,

a value of 32 (decimal) loaded into the Phase Offset Register

would produce a phase offset of 11.25o and a value of -512

would produce an offset of 180o. The phase offset is loaded via

the microprocessor interface. See the Microprocessor Write

Section on instructions for writing Control Word 4.

The most significant 18-bits from the phase adder are used

as the address a sin/cos lookup table. This lookup table

maps phase into sinusoidal amplitude. The sine and cosine

values have 18-bits of amplitude resolution. The spurious

components in the sine/cosine generation are at least

-102dBc. The sine and cosine samples are routed to the

mixer section where they are multiplied with the input

samples to translate the signal of interest to baseband.

The mixer multiplies the 14-bit input by the 18-bit quadrature

sinusoids. The mixer equations are:

The mixer output is rounded symmetrically to 15-bits.

To allow the frequency and phase of multiple parts to be

updated synchronously, two sets of registers are used for

latching the center frequency and phase offset words. The

offset phase and center frequency Control Words are first

loaded into holding registers. The contents of the holding

registers are transferred to active registers in one of two ways.

The first technique involves writing to a specific Control Word

Address. A processor write to Control Word 5, transfers the

center frequency value to the active register while a processor

write to Control Word 6 transfers the phase offset value to the

active register.

The second technique, designed for synchronizing updates to

multiple parts, uses the SYNCIN1 pin to update the active

registers. When Control Word 1, Bit 20 is set to 1, the SYNCIN1

pin causes both the center frequency and Phase Offset Holding

Registers to be transferred to active registers. Additionally,

when Control Word 0, Bit 0 is set to 1, the feedback in the

phase accumulator is zeroed when the transfer from the

holding to active register occurs. This feature provides

synchronization of the phase accumulator starting phase of

multiple parts. It can also be used to reset the phase of the

NCO synchronous with a specific event.

The carrier offset frequency is loaded using the COF and

COFSYNC pins. Figure 13 details the timing relationship

between COF, COFSYNC and CLKIN. The offset frequency

word can be zeroed if it is not needed. Similarly, the

Sample Offset Frequency Register controlling the Re-

Sampler NCO is loaded via the SOF and SOFSYNC pins.

The procedure for loading data through the two pin NCO

interfaces is identical except that the timing of SOF and

SOFSYNC is relative to PROCCLK.

Each serial word has a programmable word width of either 8,

16, 24, or 32-bits (See Control Word 0, Bits 4 and 5, for the

Carrier NCO programming and Control Word 11, Bits 3 and

4, for Timing NCO programming). On the rising edge of the

clock, data on COF or SOF is clocked into an input shift

asserting either COFSYNC or SOFSYNC “high” one CLK

period prior to the first data bit.

NOTE: Serial Data must be loaded MSB first, and COFSYNC or

SOFSYNC should not be asserted for more than one

CLK cycle.



OFF



PO 2







 PO

–





–



;

(EQ. 4)

512 to 511

–



INT 2

10

OFF

 2



HEX



–



OFF







;



(EQ. 4A)

IOUT

IIN





cos



(EQ. 5)

QOUT

IIN





sin



(EQ. 5A)

COF/

MSB

CLKIN

COFSYNC/

SOFSYNC

SOF

LSB

NOTE:

Data must be loaded MSB first.

FIGURE 13. SERIAL INPUT TIMING FOR COF AND SOF INPUTS

†Serial word width can be: 8, 16, 24, 32 bits wide.

††TD is determined by the COFSYNC, COFSYNC rate.

FIGURE 14. HOLDING REGISTERS LOAD SEQUENCE FOR

COF AND SOF SERIAL OFFSET FREQUENCY

DATA

†

DATA TRANSFERRED

TO HOLDING REGISTER

TD††

CLK TIMES

ASSERTION OF

COFSYNC, SOFSYNC

(8)

(32)

(16)

(24)

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