KMB-001LEVALZ datasheet(20/34 Pages) RENESAS

20 / 34 page

ISLA214P12

FN7982 Rev 2.00

Page 20 of 34

June 27, 2012

Analog Input

A single fully differential input (VINP/VINN) connects to the

sample and hold amplifier (SHA) of each unit A/D. The ideal

full-scale input voltage is 2.0V, centered at the VCM voltage of

0.94V as shown in Figure 27.

Best performance is obtained when the analog inputs are driven

differentially. The common-mode output voltage, VCM, should be

used to properly bias the inputs as shown in Figures 28 through

30. An RF transformer will give the best noise and distortion

performance for wideband and/or high intermediate frequency

(IF) inputs. Two different transformer input schemes are shown in

Figures 28 and 29.

This dual transformer scheme is used to improve common-mode

rejection, which keeps the common-mode level of the input

matched to VCM. The value of the shunt resistor should be

determined based on the desired load impedance. The

differential input resistance of the ISLA214P12 is 600

.

The SHA design uses a switched capacitor input stage (see

Figure 43), which creates current spikes when the sampling

capacitance is reconnected to the input voltage. This causes a

disturbance at the input which must settle before the next

sampling point. Lower source impedance will result in faster

settling and improved performance. Therefore a 2:1 or 1:1

transformer and low shunt resistance are recommended for

optimal performance.

A differential amplifier, as shown in the simplified block diagram

in Figure 30, can be used in applications that require

DC-coupling. In this configuration, the amplifier will typically

dominate the achievable SNR and distortion performance.

Intersil’s new ISL552xx differential amplifier family can also be

used in certain AC applications with minimal performance

degradation. Contact the factory for more information.

Clock Input

The clock input circuit is a differential pair (see Figure 44).

Driving these inputs with a high level (up to 1.8VP-P on each

input) sine or square wave will provide the lowest jitter

performance. A transformer with 4:1 impedance ratio will

provide increased drive levels. The clock input is functional with

AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the

lowest possible aperture jitter, it is recommended to have high

slew rate at the zero crossing of the differential clock input

signal.

The recommended drive circuit is shown in Figure 31. A duty

range of 40% to 60% is acceptable. The clock can be driven

single-ended, but this will reduce the edge rate and may impact

SNR performance. The clock inputs are internally self-biased to

AVDD/2 to facilitate AC coupling.

A selectable 2x or 4x frequency divider is provided in series with

the clock input. The divider can be used in the 2x mode with a

sample clock equal to twice the desired sample rate or in 4x

mode with a sample clock equal to four times the desired

sample rate. This allows the use of the Phase Slip feature, which

enables synchronization of multiple ADCs. The Phase Slip feature

can be used as an alternative to using the CLKDIVRST pins to

synchronize ADCs in a multiple ADC system.

FIGURE 27. ANALOG INPUT RANGE

1.0

1.8

0.6

0.2

1.4

VINP

VINN

VCM

0.94V

1.0V

FIGURE 28. TRANSFORMER INPUT FOR GENERAL PURPOSE

APPLICATIONS

ADT1-1WT

0.1µF

A/D

VCM

ADT1-1WT

1000pF

FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT FOR

HIGH IF APPLICATIONS

A / D

VCM

1000pF

TX-2-5-1

ADTL1-12

FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT

A/D

FIGURE 31. RECOMMENDED CLOCK DRIVE

TC4-19G2+

1000pF

CLKP

CLKN

0.01µF

200

1000pF

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