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KMB-001LEVALZ Datasheet(PDF) 23 Page - Renesas Technology Corp |
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KMB-001LEVALZ Datasheet(HTML) 23 Page - Renesas Technology Corp |
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23 / 34 page ![]() ISLA214P12 FN7982 Rev 2.00 Page 23 of 34 June 27, 2012 FIGURE 35. SYNCHRONOUS RESET OPERATION s1 s2 s0 s3 s1 s2 s0 s3 CLKDIVRSTP ADC1 OUTPUT DATA ADC1 CLKOUTP ADC2 CLKOUTP (phase 1) ADC2 CLKOUTP (phase 2) s1 L+td tRSTH tRSTS tRSTRT ADC2 OUTPUT DATA ANALOG INPUT SAMPLE CLOCK INPUT (CLKDIV=2) NOTES: 15. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay td. 16. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge. CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP. 17. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization. (Note 17) (Note 16) (Note 16) (Note 15) FIGURE 36. MSB-FIRST ADDRESSING CSB SCLK SDIO R/W W1 W0 A12 A11 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 A10 FIGURE 37. LSB-FIRST ADDRESSING CSB SCLK SDIO R/W W1 W0 A12 A11 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 A2 |
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