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X9521 Datasheet(PDF) 8 Page - Renesas Technology Corp

Part # X9521
Description  Dual DCP, EEPROM Memory Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
PDF  24 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

X9521 Datasheet(HTML) 8 Page - Renesas Technology Corp

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X9521
FN8207 Rev 2.00
Page 8 of 24
September 21, 2010
number of bits. Also, setting the bits (P1 = 0, P0 = 0) or (P1
= 1, P0 = 1) are reserved sequences, and will result in no
ACKNOWLEDGE after sending an Instruction Byte on
SDA.
The factory default setting of all “wiper position” settings is
with 00h stored in the NVM of the DCPs. This corresponds
to having the “wiper teminal” RWX (x=1,2) at the “lowest”
tap position, Therefore, the resistance between RWX and
RLX is a minimum (essentially only the Wiper Resistance,
RW).
DCP Read Operation
A read of DCPx (x = 1,2) can be performed using the three
byte random read command sequence shown in Figure 11.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read oper-
ation). An ACKNOWLEDGE is returned by the X9521 after
the Slave Address if received correctly. Next, an Instruction
Byte is issued on SDA. Bits P1 - P0 of the Instruction Byte
determine which DCP “wiper position” is to be read. In this
case, the state of the WT bit is “don’t care”. If the Instruction
Byte format is valid, then another ACKNOWLEDGE is
returned by the X9521.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave address
byte with the R/W bit set to 1. Then the X9521 issues an
ACKNOWLEDGE followed by Data Byte, and finally, the
master issues a STOP condition. The Data Byte read in
this operation, corresponds to the “wiper position” (value of
the WCR) of the DCP pointed to by bits P1 and P0.
It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 11).
S
t
a
r
t
S
t
o
p
Slave
Address
Address
Byte
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
Data
(1)
A
C
K
(2 < n < 16)
Figure 10. EEPROM Page Write Operation
1 01 0 0 0 0 0
Slave
Address
Instruction
Byte
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data Byte
A
C
K
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
Figure 11. DCP Read Sequence
“Dummy” write
READ Operation
10 1 1 11 0
0
00 00
0
W
T
P
1
P
0
10 1 1 11 1
0
WRITE Operation
-
MSB
LSB
DCPx
x = 1
x = 2
“-” = DON’T CARE



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