DS2761AX datasheet(4/24 Pages) DALLAS

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DS2761

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Table 1. DETAILED PIN DESCRIPTION

SYMBOL

TSSOP

FLIP

CHIP

DESCRIPTION

1C1

Charge Protection Control Output. Controls an external p-channel

high-side charge protection FET.

3B2

Discharge Protection Control Output. Controls an external p-channel

high-side discharge protection FET.

Data Input/Out. 1-Wire data line. Open-drain output driver. Connect

this pin to the DATA terminal of the battery pack. Pin has an internal

mA pull-down for sensing disconnection.

PIO

Programmable I/O Pin. Used to control and monitor user-defined

external circuitry. Open drain to VSS.

PLS

Battery Pack Positive Terminal Input. The DS2761 monitors the pack

plus terminal through PLS to detect overcurrent and overload conditions,

as well as the presence of a charge source. Additionally, a charge path to

recover a deeply depleted cell is provided from PLS to VDD. In sleep

mode (with SWEN = 0), any capacitance or voltage source connected to

PLS is discharged internally to VSS through 200

mA (nominal) to assure

reliable detection of a valid charge source. For details of other internal

connections to PLS and associated conditions see the Li+ Protection

Circuitry section.

Power Switch Sense Input. The device wakes up from Sleep Mode

when it senses the closure of a switch to VSS on this pin. Pin has an

internal 1

mA pull-up to VDD.

VIN

Voltage Sense Input. The voltage of the Li+ cell is monitored via this

input pin. This pin has a weak pullup to VDD.

VDD

Power Supply Input. Connect to the positive terminal of the Li+ cell

through a decoupling network.

VSS

13,14,

Device Ground. Connect directly to the negative terminal of the Li+ cell.

For the external sense resistor configuration, connect the sense resistor

between VSS and SNS.

SNS

4,5,6

Sense Resistor Connection. Connect to the negative terminal of the

battery pack. In the internal sense resistor configuration, the sense resistor

is connected between VSS and SNS.

IS1

Current Sense Input. This pin is internally connected to VSS through a

4.7k

W resistor. Connect a 0.1mF capacitor between IS1 and IS2 to

complete a low-pass input filter.

IS2

Current Sense Input. This pin is internally connected to SNS through a

4.7k

W resistor.

SNS

Probe

N/A

Do Not Connect.

VSS

Probe

N/A

Do Not Connect.

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