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LTC1748CFW Datasheet(PDF) 9 Page - Linear Technology

Part # LTC1748CFW
Description  14-Bit, 80Msps Low Noise ADC
PDF  20 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC1748CFW Datasheet(HTML) 9 Page - Linear Technology

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LTC1748
1748fa
PI FU CTIO S
SENSE (Pin 1): Reference Sense Pin. Ground selects
±1V.
VDD selects ±1.6V. Greater than 1V and less than 1.6V
applied to the SENSE pin selects an input range of
±VSENSE,
±1.6V is the largest valid input range.
VCM (Pin 2): 2.35V Output and Input Common Mode Bias.
Bypass to ground with 4.7
µF ceramic chip capacitor.
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC Power
Ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN– (Pin 5): Negative Differential Analog Input.
VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND
with 1
µF ceramic chip capacitors at Pin 8 and Pin 18.
REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11
with 0.1
µF ceramic chip capacitor. Do not connect to
Pin 14.
REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with
0.1
µFceramicchipcapacitor,toPin14witha4.7µFceramic
capacitor and to ground with 1
µF ceramic capacitor.
REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with
0.1
µF ceramic chip capacitor, to Pin 11 with a 4.7µF ce-
ramic capacitor and to ground with 1
µF ceramic capacitor.
REFHB (Pin 15): ADC High Reference. Bypass to Pin 14
with 0.1
µF ceramic chip capacitor. Do not connect to
Pin 11.
MSBINV (Pin 22): MSB Inversion Control. Low inverts
the MSB, 2’s complement output format. High does not
invert the MSB, offset binary output format.
ENC (Pin 23): Encode Input. The input sample starts on the
positive edge.
ENC (Pin 24): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1
µF
ceramic for single-ended ENCODE signal.
OE (Pin 25): Output Enable. Low enables outputs. Logic
high makes outputs Hi-Z. OE should not exceed the
votlage on OVDD.
CLKOUT (Pin 26): Data Valid Output. Latch data on the
rising edge of CLKOUT.
OGND (Pins 27, 38, 47): Output Driver Ground.
D0-D3 (Pins 28 to 31): Digital Outputs.
OVDD (Pins 32, 43): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1
µF ceramic chip capacitor.
D4-D6 (Pins 33 to 35): Digital Outputs.
D7-D10 (Pins 39 to 42): Digital Outputs.
D11-D13 (Pins 44 to 46): Digital Outputs.
OF (Pin 48): Over/Under Flow Output. High when an over
or under flow has occurred.
Supply Current vs Sample Rate
SAMPLE RATE (Msps)
0
280
290
300
80
1748 G32
270
260
20
40
60
100
250
240
230
TA = 25°C
TYPICAL PERFOR A CE CHARACTERISTICS
Offset and Gain Error
vs Temperature
TEMPERATURE (
°C)
–50
6
GAIN ERROR
OFFSET ERROR
10
1748 G35
0
–4
–30
–10
30
–6
–8
8
4
2
–2
50
70
90



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