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M69AW024B Datasheet(PDF) 13 Page - STMicroelectronics

Part # M69AW024B
Description  16 Mbit (1M x16) 3V Asynchronous PSRAM
PDF  29 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M69AW024B Datasheet(HTML) 13 Page - STMicroelectronics

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M69AW024B
Table 7. Read and Standby Modes AC Characteristics
Symbol
Alt.
Parameter
M69AW024B
Unit
–60
–70
Min
Max
Min
Max
tAVAX
tRC
Read Cycle Time
80
90
ns
tAVEH
tRC
Address Valid to Chip Enable High (Read Cycle
Time)
80
90
ns
tAVEL
(5)
tASC
Address Set-up Time to Chip Enable Low
–5
–5
ns
tAVGH
tRC
Address Valid to Output Enable High (Read Cycle
Time)
80
90
ns
tAVGL1
(3,6)
tASO
Address Valid to Output Enable Low
25
30
ns
tAVGL2
(7)
tASO(ABS) Address Valid to Output Enable Low (absolute)
5
5
ns
tAVQV
(1,4)
tAA
Address Access Time
60
70
ns
tAXAV
(4,8)
tAX
Address Invalid Time
5
5
ns
tAXQX
(1)
tOH
Output Hold Time after Address Transition
5
5
ns
tBLEL
(5)
tBSC
LB, UB Set-up Time to Chip Enable Low
–5
–5
ns
tBLGL
tBSO
LB, UB Set-up Time to Output Enable Low
0
0
ns
tEHAX
tCHAH
Chip Enable High to Address Hold Time
–5
–5
ns
tEHBH
tCHBH
Chip Enable High to LB, UB High
–5
–5
ns
tEHEL
tCP
Chip Enable High Pulse Width
10
12
ns
tEHQX
(1)
tOH
Output Hold Time after Chip Enable Low
5
5
ns
tEHQZ
(2)
tCHZ
Chip Enable High to Output Hi-Z
20
25
ns
tELAX
(4)
tCLAH
Chip Enable Low to Address Hold Time
80
90
ns
tELEH
tRC
Chip Enable Low to Chip Enable High (Read Cycle
Time)
80
90
ns
tELGH
tRC
Chip Enable Low to Output Enable High (Read
Cycle Time)
80
90
ns
tELGL
(3,6,9,10)
tCLOL
Chip Enable Low to Output Enable Low Delay Time
25
1000
30
1000
ns
tELQV
(1,3)
tCE
Chip Enable Access Time
60
70
ns
tELQX
(2)
tCLZ
Chip Enable Low to Output Lo-Z
5
5
ns
tGHAX
tOHAH
Output Enable High to Address Hold Time
–5
–5
ns
tGHBH
tOHBH
Output Enable High to LB, UB High
–5
–5
ns
tGHGL1
(6,9,10)
tOP
Output Enable High Pulse Width
25
1000
30
1000
ns
tGHGL2
(7)
tOP(ABS)
Output Enable High Pulse Width (absolute)
10
10
ns
tGHQX
(1)
tOH
Output Hold Time after Output Enable Low
5
5
ns
tGHQZ
(2)
tOHZ
Output Enable High to Output Hi-Z
20
25
ns
tGLAX
(4,9)
tOLAH
Output Enable Low to Address Hold Time
45
50
ns
tGLEH
(9)
tOLCH
Output Enable Low to Chip Enable High Delay Time
45
50
ns



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