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AC-Coupled Interface to ADC/DAC

DAC

CDCM7005

YxA

YxB

LVPECL

Driver

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

The generation of the two required clock signals (data input clock, clock for DAC) for such an interpolating DAC

can be done in different ways. The recommended way is to use the CDCM7005, which generates the fast

sampling clock for the DAC from the data input clock signal. The DAC5687 demands that the edges of the two

input clocks must be phase aligned within

±500 ps for latching the data properly. This phase alignment is well

achieved with the CDCM7005, which assures a maximum skew of 70 ps of the different different outputs to each

other.

Another advantage of this clock solution is that the ADC or DAC can be driven directly in an ac-coupling interface

as shown in Figure 27, with an external termination in a differential configuration. There is no need for a

transformer to generate a differential signal from a single-ended clock source.

Figure 27. Driving DAC or ADC With PECL Output of the CDCM7005

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