SCF5250 datasheet(12/48 Pages) MOTOROLA

12 / 48 page

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Signal Descriptions

Freescale Semiconductor

4.2

GPIO

Many pins have an optional GPIO function.

•

General purpose input is always active, regardless of state of pin.

•

General purpose output or primary output is determined by the appropriate setting of the Pin

Multiplex Control Registers, GPIO-FUNCTION, GPIO1-FUNCTION and PIN-CONFIG.

•

At Power-on reset, all pins are set to their primary function.

4.3

SCF5250 Bus Signals

These signals provide the external bus interface to the SCF5250.

Linear regulator input

LININ

Input, typically I/O supply (3.3V)

Linear regulator ground

LINGND

High Impedance

HI-Z

Assertion Tri-states all output signal

pins.

Debug Data

DDATA0/CTS1/SDATA0_SDIO1/GPIO1

DDATA1/RTS1/SDATA2_BS2/GPIO2

DDATA2/CTS0/GPIO3

DDATA3/RTS0/GPIO4

Displays captured processor data and

break-point status.

In/Out

Hi-Z

Processor Status

PST0/GPIO50

PST1/GPIO49

PST2/INTMON2/GPIO48

PST3/INTMON1/GPIO47

Indicates internal processor status.

In/Out

Hi-Z

Processor clock

PSTCLK/GPIO51

processor clock output

Out

Test Clock

TCK

Clock signal for IEEE 1149.1A JTAG.

Test Reset/Development

Serial Clock

TRST/DSCLK

Multiplexed signal that is

asynchronous reset for JTAG

controller. Clock input for debug

module.

Test Mode Select/ Break

Point

TMS/BKPT

Multiplexed signal that is test mode

select in JTAG mode and a hardware

break-point in debug mode.

Test Data Input /

Development Serial Input

TDI/DSI

Multiplexed serial input for the JTAG or

background debug module.

Test Data

Output/Development Serial

Output

TDO/DSO

Multiplexed serial output for the JTAG

or background debug module.

Out

Table 3. SCF5250 Signal Index (continued)

Signal Name

Mnemonic

Function

Input/

Output

Reset

State

SCF5250 Datasheet(PDF) 12 Page - Motorola, Inc

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