SCF5250 datasheet(20/48 Pages) MOTOROLA

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SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Signal Descriptions

Freescale Semiconductor

4.19.4 Debug Data

The debug data pins, DDATA0/CTS1/SDATA0_SDIO1/GPIO1, DDATA1/RTS1/SDATA2_BS2/GPIO2,

DDATA2/CTS0/GPIO3, and DDATA3/RTS0/GPIO4, are four bits wide. This nibble-wide bus displays

captured processor data and break-point status.

4.19.5 Processor Status

The processor status pins, PST0/GPIO50, PST1/GPIO49, PST2/INTMON/GPIO48, and

PST3/INTMON/GPIO47, indicate the SCF5250 processor status. During debug mode, the timing is

synchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer.

Table 13 shows the encodings of these signals.

Table 13. Processor Status Signal Encodings

PST[3:0]

Definition

(HEX)

(BINARY)

0000

Continue execution

0001

Begin execution of an instruction

0010

Reserved

0011

Entry into user-mode

0100

Begin execution of PULSE and WDDATA instructions

0101

Begin execution of taken branch or Synch_PC1

0110

Reserved

0111

Begin execution of RTE instruction

1000

Begin 1-byte data transfer on DDATA

1001

Begin 2-byte data transfer on DDATA

1010

Begin 3-byte data transfer on DDATA

1011

Begin 4-byte data transfer on DDATA

1100

Exception processing2

1101

Emulator mode entry exception processing2

1110

Processor is stopped, waiting for interrupt2

1111

Processor is halted2

Rev. B enhancement.

These encodings are asserted for multiple cycles.

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