AD9544SLASHPCBZ datasheet(26/62 Pages) AD

26 / 62 page

AD9544

Data Sheet

Rev. 0 | Page 26 of 62

TERMINOLOGY

Zero Delay

Zero delay is seen in an integer-N PLL architecture that establishes

zero (or nearly zero, but constant) phase offset between the final

output signal and the signal appearing at the reference input of

the PLL phase detector. A PLL with zero delay provides minimal

input to output phase offset in the static (steady state) sense.

That is, phase slewing at the output typically occurs any time

the PLL is in the process of phase or frequency acquisition (for

example, when a multiple input PLL switches from one input

reference signal to another).

Hitless Switchover

Hitless switchover applies to PLLs with the ability to switch

from one reference signal to another while maintaining a

constant phase relationship from the active input to output.

Hitless switchover is the ability of a PLL to switch between

reference signals having an arbitrary initial instantaneous

phase offset. In hitless switching, the output signal slews in a

prescribed manner from its initial phase to the new phase, and

the absolute phase relationship from active input to output is

maintained. The reference switching scheme is hitless if the

phase slewing is gradual enough to not cause traffic hits caused

by the output clock phase slewing. A PLL employing hitless

switchover capability requires the output/input frequency ratio

to be an integer greater than or equal to 1. Hitless output phase

transient limitation applies any time the PLL is in the process of

phase or frequency acquisition (that is, it is not necessarily

limited to reference switching).

Phase Buildout (PBO) Switchover

PBO only applies to PLLs with the ability to switch from

one reference signal to another. PBO is the ability of a PLL to

switch between two reference signals having an arbitrary initial

instantaneous phase offset, whereby the phase of the output

signal remains fixed. This mode of operation implies the ability

of the PLL to absorb the phase difference between the two

reference input signals, the goal being to prevent a phase

disturbance at the output when switching between two

reference signals. Prevention of a phase disturbance at the

output means there is no guarantee of phase alignment between

the input and output signals. Unlike hitless switchover, PBO

places no restriction on the output/input frequency ratio. PBO

output phase transient prevention applies any time the PLL is in

the process of phase or frequency acquisition (that is, it is not

necessarily limited to reference switching).

For more information, see the AN-1420 Application Note, Phase

Buildout and Hitless Switchover with Digital Phase-Locked Loops

(DPLLs).

AD9544/PCBZ Datasheet(PDF) 26 Page - Analog Devices

AD9544/PCBZ Datasheet(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL