AD9544SLASHPCBZ datasheet(29/62 Pages) AD

29 / 62 page

Data Sheet

AD9544

Rev. 0 | Page 29 of 62

CLOCK OUTPUTS

AD9544

PLLx

+1.8V

QXY

QXYY

I-SOURCE MODE

OUTxyP

OUTxyN

50Ω

100Ω

50Ω

0.1µF

LVDS OR

LVPECL

RECEIVER

LVDS: USE 7.5mA DRIVER SETTING.

LVPECL: USE 15mA DRIVER SETTING.

Figure 31. LVDS-Compatible Output Swing, AC-Coupled (V p-p ≈ 375 mV per Section for I = 15 mA

AD9544

PLLx

+1.8V

QXY

QXYY

I-SOURCE MODE

OUTxyP

OUTxyN

50Ω

TO HCSL

RECEIVER

Figure 32. HCSL Output, V p-p ≈ 750 mV per Section (I = 15 mA)

AD9544

PLLx

QXY

QXYY

I-SINK MODE

OUTxyP

OUTxyN

50Ω

1.2V, 1.5V

OR 1.8V

Figure 33. CML Output (I = 7.5 mA; I = 15 mA Options for 1.5 V or 1.8 V Supply)

AD9544

PLLx

QXY

QXYY

I-SINK MODE

OUTxyP

OUTxyN

50Ω

1.8V

10nF

Figure 34. LVDS-Compatible Output, 1.24 V Common-Mode, T Network

(I = 7.5 mA; I = 15 mA with Extra 100 Ω Termination, RL)

AD9544

PLLx

QXY

QXYY

I-SINK MODE

OUTxyP

OUTxyN

1.8V

63.4Ω 237Ω

Figure 35. LVDS-Compatible Output, 1.2 V Common-Mode, Thevenin Bias

Network (I = 7.5 mA; 15 mA With Extra 100 Ω Termination, RL)

AD9544

PLLx

QXY

QXYY

I-SINK MODE

OUTxyP

OUTxyN

1.8V

56.2Ω 453Ω

Figure 36. 2.5 V LVPECL or Double Amplitude LVDS-Compatible Boost

Output, 1.5 V p-p, 1.24 V Common-Mode (I = 15 mA)

AD9544

PLLx

QXY

QXYY

I-SOURCE MODE

OUTxyP

OUTxyN

+1.8V

IN PHASE

OUTPUTS

Figure 37. Single-Divider, Single-Ended Mode Providing In-Phase Outputs

(Current Source Mode)

AD9544

PLLx

QXY

QXYY

I-SOURCE MODE

OUTxyP

OUTxyN

+1.8V

INDEPENDENT

OUTPUTS

Figure 38. Dual-Divider, Single-Ended Mode Providing Independent Outputs

(Current Source Mode); Note that Single-Ended CML Mode Is Also Available

(See Figure 33)

AD9544/PCBZ Datasheet(PDF) 29 Page - Analog Devices

AD9544/PCBZ Datasheet(HTML) 29 Page - Analog Devices

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