November 22, 2004

16

Philips Semiconductors

Preliminary specification

Universal LCD driver

for low multiplex rates

PCF8562

7-segment numeric display showing all drive modes is given in Fig.10; the RAM filling organization depicted applies

equally to other LCD types.

With reference to Fig.10, in the static drive mode, the eight transmitted data bits are placed in bit 0 of eight successive

display RAM addresses. In the 1 : 2 mode, the eight transmitted data bits are placed in bits 0 and 1 of four successive

display RAM addresses. In the 1 : 3 mode, these bits are placed in bits 0, 1 and 2 of three successive addresses, with

bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this

address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted.

In the 1 : 4 mode, the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM

addresses.

6.11

Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual

display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with

the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte is stored

at the display RAM address indicated by the data pointer in accordance with the filling order shown in Fig.11. After each

byte is stored, the contents of the data pointer are automatically incremented by a value dependent on the selected LCD

is terminated early then the state of the data pointer will be unknown. The data pointer should be re-written prior to further

RAM accesses.

6.12

Device Select

Storage is allowed to take place when the internal select register agrees with the hardware subaddress applied to A0,

A1 and A2.

6.13

Output bank selector

The output bank selector selects one of the four bits per display RAM address for transfer to the display latch. The actual

bit chosen depends on the selected LCD drive mode and on the instant in the multiplex sequence. In 1 : 4 mode, all RAM

addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 mode,

bits 0, 1 and 2 are selected sequentially. In 1 : 2 mode, bits 0 and 1 are selected and, in static mode, bit 0 is selected.

Signal SYNC will reset these sequences to the following starting points; bit 3 for 1 : 4 mode, bit 2 for 1 : 3 mode, bit 1

for 1 : 2 mode and bit 0 for static mode.

Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses and

segment outputs also between bits in a RAM word and the backplane outputs.

0

0

1

2

3

1

2

3

4

27

28

29

30

31

display RAM addresses (rows) / segment outputs (S)

display RAM bits

(columns) /

backplane outputs

(BP)

MBE525v2